EDN Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.380s	18.922us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.020s	25.151us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.050s	15.261us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.950s	2.369ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.340s	40.481us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.920s	31.942us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.050s	15.261us	20	20	100.00
		edn_csr_aliasing	1.340s	40.481us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.111m	3.014ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.111m	3.014ms	300	300	100.00
V2	genbits	edn_genbits	1.111m	3.014ms	300	300	100.00
V2	interrupts	edn_intr	1.430s	22.351us	50	50	100.00
V2	alerts	edn_alert	1.740s	101.295us	200	200	100.00
V2	errs	edn_err	1.650s	27.272us	100	100	100.00
V2	disable	edn_disable	1.230s	13.562us	50	50	100.00
		edn_disable_auto_req_mode	1.870s	119.187us	50	50	100.00
V2	stress_all	edn_stress_all	7.800s	412.360us	50	50	100.00
V2	intr_test	edn_intr_test	1.170s	15.687us	50	50	100.00
V2	alert_test	edn_alert_test	1.800s	122.993us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.380s	121.223us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.380s	121.223us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.020s	25.151us	5	5	100.00
		edn_csr_rw	1.050s	15.261us	20	20	100.00
		edn_csr_aliasing	1.340s	40.481us	5	5	100.00
		edn_same_csr_outstanding	1.740s	111.907us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.020s	25.151us	5	5	100.00
		edn_csr_rw	1.050s	15.261us	20	20	100.00
		edn_csr_aliasing	1.340s	40.481us	5	5	100.00
		edn_same_csr_outstanding	1.740s	111.907us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	8.670s	1.601ms	5	5	100.00
		edn_tl_intg_err	2.940s	96.423us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.320s	18.654us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.740s	101.295us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.670s	1.601ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.670s	1.601ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.670s	1.601ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.670s	1.601ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.740s	101.295us	200	200	100.00
		edn_sec_cm	8.670s	1.601ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.740s	101.295us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.940s	96.423us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.688h	10.000s	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1106	1130	97.88

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.86	98.87	94.23	97.02	91.86	96.33	99.78	92.94

Failure Buckets

• Job timed out after * minutes has 22 failures:

  • Test edn_stress_all_with_rand_reset has 22 failures.

    • 2.edn_stress_all_with_rand_reset.2789108578050501117669626685876279451466023401547080169027372901472318669719
      Log /nightly/current_run/scratch/master/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 5.edn_stress_all_with_rand_reset.24484490487974741408643425839624556716962482890937451880507944879025150652931
      Log /nightly/current_run/scratch/master/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 20 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 0.edn_stress_all_with_rand_reset.27230472684526788840330087138541704477128341504206463741195578950034421799363
      Line 261, in log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:849) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 3.edn_stress_all_with_rand_reset.101929276075858348434696323242786874686745865397419452452028942176165747399434
      Line 148, in log /nightly/current_run/scratch/master/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1658991556 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1658991556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---