HMAC Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.140s	3.851ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.130s	44.143us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.250s	116.723us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.670s	1.220ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.230s	153.373us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.312m	628.534ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.250s	116.723us	20	20	100.00
		hmac_csr_aliasing	7.230s	153.373us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.515m	5.061ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.799m	1.509ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	5.128m	27.032ms	30	30	100.00
		hmac_test_sha384_vectors	9.313m	51.682ms	75	75	100.00
		hmac_test_sha512_vectors	8.861m	27.764ms	75	75	100.00
		hmac_test_hmac256_vectors	16.690s	2.650ms	50	50	100.00
		hmac_test_hmac384_vectors	19.530s	384.125us	60	60	100.00
		hmac_test_hmac512_vectors	19.840s	1.669ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	38.640s	2.893ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	23.002m	7.122ms	10	10	100.00
V2	error	hmac_error	1.895m	78.704ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.936m	27.769ms	10	10	100.00
V2	save_and_restore	hmac_smoke	15.140s	3.851ms	10	10	100.00
		hmac_long_msg	1.515m	5.061ms	10	10	100.00
		hmac_back_pressure	1.799m	1.509ms	25	25	100.00
		hmac_datapath_stress	23.002m	7.122ms	10	10	100.00
		hmac_burst_wr	38.640s	2.893ms	50	50	100.00
		hmac_stress_all	43.513m	207.085ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.140s	3.851ms	10	10	100.00
		hmac_long_msg	1.515m	5.061ms	10	10	100.00
		hmac_back_pressure	1.799m	1.509ms	25	25	100.00
		hmac_datapath_stress	23.002m	7.122ms	10	10	100.00
		hmac_wipe_secret	1.936m	27.769ms	10	10	100.00
		hmac_test_sha256_vectors	5.128m	27.032ms	30	30	100.00
		hmac_test_sha384_vectors	9.313m	51.682ms	75	75	100.00
		hmac_test_sha512_vectors	8.861m	27.764ms	75	75	100.00
		hmac_test_hmac256_vectors	16.690s	2.650ms	50	50	100.00
		hmac_test_hmac384_vectors	19.530s	384.125us	60	60	100.00
		hmac_test_hmac512_vectors	19.840s	1.669ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.140s	3.851ms	10	10	100.00
		hmac_long_msg	1.515m	5.061ms	10	10	100.00
		hmac_back_pressure	1.799m	1.509ms	25	25	100.00
		hmac_datapath_stress	23.002m	7.122ms	10	10	100.00
		hmac_burst_wr	38.640s	2.893ms	50	50	100.00
		hmac_error	1.895m	78.704ms	10	10	100.00
		hmac_wipe_secret	1.936m	27.769ms	10	10	100.00
		hmac_test_sha256_vectors	5.128m	27.032ms	30	30	100.00
		hmac_test_sha384_vectors	9.313m	51.682ms	75	75	100.00
		hmac_test_sha512_vectors	8.861m	27.764ms	75	75	100.00
		hmac_test_hmac256_vectors	16.690s	2.650ms	50	50	100.00
		hmac_test_hmac384_vectors	19.530s	384.125us	60	60	100.00
		hmac_test_hmac512_vectors	19.840s	1.669ms	75	75	100.00
		hmac_stress_all	43.513m	207.085ms	50	50	100.00
V2	stress_all	hmac_stress_all	43.513m	207.085ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.880s	24.959us	50	50	100.00
V2	intr_test	hmac_intr_test	0.920s	17.821us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.180s	472.830us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.180s	472.830us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.130s	44.143us	5	5	100.00
		hmac_csr_rw	1.250s	116.723us	20	20	100.00
		hmac_csr_aliasing	7.230s	153.373us	5	5	100.00
		hmac_same_csr_outstanding	3.120s	758.196us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.130s	44.143us	5	5	100.00
		hmac_csr_rw	1.250s	116.723us	20	20	100.00
		hmac_csr_aliasing	7.230s	153.373us	5	5	100.00
		hmac_same_csr_outstanding	3.120s	758.196us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.360s	222.351us	5	5	100.00
		hmac_tl_intg_err	5.270s	252.574us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.270s	252.574us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.140s	3.851ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.200s	110.714us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	10.148m	28.497ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.390s	167.726us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.86	99.79	96.74	100.00	100.00	99.67	99.52	47.30