KEYMGR Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	37.150s	5.955ms	50	50	100.00
V1	random	keymgr_random	42.050s	2.999ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.200s	33.884us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.440s	26.906us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.270s	1.045ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.790s	1.391ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.980s	78.392us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.440s	26.906us	20	20	100.00
		keymgr_csr_aliasing	9.790s	1.391ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.320m	1.900ms	50	50	100.00
V2	sideload	keymgr_sideload	17.810s	2.371ms	50	50	100.00
		keymgr_sideload_kmac	57.010s	6.897ms	49	50	98.00
		keymgr_sideload_aes	45.510s	10.795ms	50	50	100.00
		keymgr_sideload_otbn	39.150s	4.434ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	20.060s	1.359ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.220s	530.687us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.300s	490.206us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	46.710s	1.853ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	57.920s	8.259ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	4.010s	883.431us	50	50	100.00
V2	stress_all	keymgr_stress_all	2.415m	14.060ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.980s	18.958us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.230s	18.134us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.640s	2.326ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.640s	2.326ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.200s	33.884us	5	5	100.00
		keymgr_csr_rw	1.440s	26.906us	20	20	100.00
		keymgr_csr_aliasing	9.790s	1.391ms	5	5	100.00
		keymgr_same_csr_outstanding	3.450s	118.476us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.200s	33.884us	5	5	100.00
		keymgr_csr_rw	1.440s	26.906us	20	20	100.00
		keymgr_csr_aliasing	9.790s	1.391ms	5	5	100.00
		keymgr_same_csr_outstanding	3.450s	118.476us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
		keymgr_tl_intg_err	4.790s	388.726us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.900s	923.163us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.900s	923.163us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.900s	923.163us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.900s	923.163us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.750s	1.060ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.790s	388.726us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.900s	923.163us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.320m	1.900ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	42.050s	2.999ms	50	50	100.00
		keymgr_csr_rw	1.440s	26.906us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	42.050s	2.999ms	50	50	100.00
		keymgr_csr_rw	1.440s	26.906us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	42.050s	2.999ms	50	50	100.00
		keymgr_csr_rw	1.440s	26.906us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.220s	530.687us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	57.920s	8.259ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	57.920s	8.259ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	42.050s	2.999ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.270s	1.529ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	27.360s	1.399ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.220s	530.687us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	27.360s	1.399ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	27.360s	1.399ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	27.360s	1.399ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.570s	2.005ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	27.360s	1.399ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.140s	1.392ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1085	1110	97.75

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.80	99.13	97.99	98.69	100.00	99.01	98.63	91.16

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test keymgr_stress_all_with_rand_reset has 22 failures.

    • 3.keymgr_stress_all_with_rand_reset.45296006838108279372704948255915765676912093983506775355534854090346756214445
      Line 180, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 291620649 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 291620649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.keymgr_stress_all_with_rand_reset.29048014278308002463889864307569818461589536243995731205517601096072795835495
      Line 335, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 129018398 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 129018398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all has 1 failures.

    • 16.keymgr_stress_all.30813296642140600048124199782076899489210706639979540537276811561212634832202
      Line 4159, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 5411935685 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 5411935685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_kmac has 1 failures.

    • 21.keymgr_sideload_kmac.40239354353675732824077119177498357586605579046219619229254668551287796448636
      Line 114, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest/run.log

        UVM_ERROR @  31879770 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @  31879770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:849) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 29.keymgr_stress_all_with_rand_reset.92895010027472197501809070385799974395950074651518544674141613446163222893685
      Line 680, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1306212462 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1306212462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---