KMAC/MASKED Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.422m	6.820ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.480s	44.226us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.550s	118.669us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.360s	5.774ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.140s	144.079us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.230s	1.469ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.550s	118.669us	20	20	100.00
		kmac_csr_aliasing	7.140s	144.079us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.090s	11.967us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.610s	116.373us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.043h	520.051ms	50	50	100.00
V2	burst_write	kmac_burst_write	21.925m	14.773ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.844m	326.386ms	5	5	100.00
		kmac_test_vectors_sha3_256	39.541m	486.461ms	5	5	100.00
		kmac_test_vectors_sha3_384	25.496m	281.918ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.447m	163.122ms	5	5	100.00
		kmac_test_vectors_shake_128	36.884m	307.046ms	5	5	100.00
		kmac_test_vectors_shake_256	32.058m	61.715ms	5	5	100.00
		kmac_test_vectors_kmac	2.990s	497.178us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.860s	151.330us	5	5	100.00
V2	sideload	kmac_sideload	7.907m	15.364ms	50	50	100.00
V2	app	kmac_app	6.133m	18.617ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.927m	71.967ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.501m	374.923ms	50	50	100.00
V2	error	kmac_error	8.397m	138.634ms	50	50	100.00
V2	key_error	kmac_key_error	18.580s	6.223ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.780s	289.786us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.840s	10.279ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	27.420s	918.281us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.336m	19.027ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.590s	778.974us	50	50	100.00
V2	stress_all	kmac_stress_all	41.118m	145.248ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.180s	19.346us	50	50	100.00
V2	alert_test	kmac_alert_test	1.370s	52.026us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.980s	850.283us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.980s	850.283us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.480s	44.226us	5	5	100.00
		kmac_csr_rw	1.550s	118.669us	20	20	100.00
		kmac_csr_aliasing	7.140s	144.079us	5	5	100.00
		kmac_same_csr_outstanding	2.570s	140.500us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.480s	44.226us	5	5	100.00
		kmac_csr_rw	1.550s	118.669us	20	20	100.00
		kmac_csr_aliasing	7.140s	144.079us	5	5	100.00
		kmac_same_csr_outstanding	2.570s	140.500us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.610s	447.216us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.610s	447.216us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.610s	447.216us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.610s	447.216us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.550s	2.093ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.939m	86.362ms	5	5	100.00
		kmac_tl_intg_err	5.450s	952.578us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.450s	952.578us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.590s	778.974us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.422m	6.820ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.907m	15.364ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.610s	447.216us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.939m	86.362ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.939m	86.362ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.939m	86.362ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.422m	6.820ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.590s	778.974us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.939m	86.362ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.976m	103.359ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.422m	6.820ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.043m	5.290ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			938	940	99.79

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.37	99.27	94.49	99.89	79.58	97.15	99.38	97.86

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:525) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 4.kmac_stress_all_with_rand_reset.30434510081892099164942486688801355764530721838686274075988685494322920329983
      Line 210, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2971334712 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 2971334712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.kmac_stress_all_with_rand_reset.28898825805103583582917723336737390792707224143632986157141384770331521647211
      Line 217, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 900963666 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 900963666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---