OTBN Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 12.000s 46.705us 0 1 0.00
V1 single_binary otbn_single 34.000s 396.099us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 9.000s 18.378us 5 5 100.00
V1 csr_rw otbn_csr_rw 8.000s 27.536us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 10.000s 284.126us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 9.000s 27.588us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 12.000s 63.551us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 8.000s 27.536us 20 20 100.00
otbn_csr_aliasing 9.000s 27.588us 5 5 100.00
V1 mem_walk otbn_mem_walk 39.000s 1.448ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 23.000s 376.076us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 54.000s 724.654us 0 10 0.00
V2 multi_error otbn_multi_err 50.000s 318.805us 0 1 0.00
V2 back_to_back otbn_multi 1.483m 684.628us 0 10 0.00
V2 stress_all otbn_stress_all 52.000s 322.884us 0 10 0.00
V2 lc_escalation otbn_escalate 17.000s 77.398us 18 60 30.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 82.522us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 20.000s 69.294us 0 10 0.00
V2 alert_test otbn_alert_test 15.000s 62.292us 50 50 100.00
V2 intr_test otbn_intr_test 9.000s 17.790us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 14.000s 117.775us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 14.000s 117.775us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 9.000s 18.378us 5 5 100.00
otbn_csr_rw 8.000s 27.536us 20 20 100.00
otbn_csr_aliasing 9.000s 27.588us 5 5 100.00
otbn_same_csr_outstanding 8.000s 89.475us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 9.000s 18.378us 5 5 100.00
otbn_csr_rw 8.000s 27.536us 20 20 100.00
otbn_csr_aliasing 9.000s 27.588us 5 5 100.00
otbn_same_csr_outstanding 8.000s 89.475us 20 20 100.00
V2 TOTAL 162 246 65.85
V2S mem_integrity otbn_imem_err 16.000s 49.525us 2 10 20.00
otbn_dmem_err 15.000s 58.245us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 19.000s 66.720us 0 5 0.00
otbn_controller_ispr_rdata_err 2.700m 755.500us 0 5 0.00
otbn_mac_bignum_acc_err 12.000s 116.891us 0 5 0.00
otbn_urnd_err 5.000s 25.656us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 17.814us 4 5 80.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 9.000s 25.546us 1 2 50.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 8.000s 24.395us 9 10 90.00
V2S tl_intg_err otbn_sec_cm 4.050m 1.537ms 2 5 40.00
otbn_tl_intg_err 27.000s 100.614us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 40.000s 171.517us 16 20 80.00
V2S prim_fsm_check otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S prim_count_check otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_mem_scramble otbn_smoke 12.000s 46.705us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 15.000s 58.245us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 16.000s 49.525us 2 10 20.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 27.000s 100.614us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 17.000s 77.398us 18 60 30.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 16.000s 49.525us 2 10 20.00
otbn_dmem_err 15.000s 58.245us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 82.522us 4 5 80.00
otbn_illegal_mem_acc 8.000s 17.814us 4 5 80.00
otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_scramble_key_sideload otbn_single 34.000s 396.099us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 16.000s 49.525us 2 10 20.00
otbn_dmem_err 15.000s 58.245us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 82.522us 4 5 80.00
otbn_illegal_mem_acc 8.000s 17.814us 4 5 80.00
otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 17.000s 77.398us 18 60 30.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 16.000s 49.525us 2 10 20.00
otbn_dmem_err 15.000s 58.245us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 82.522us 4 5 80.00
otbn_illegal_mem_acc 8.000s 17.814us 4 5 80.00
otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_data_reg_sw_sca otbn_single 34.000s 396.099us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 27.000s 94.509us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 11.000s 151.478us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.417m 386.695us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.417m 386.695us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 10.000s 93.650us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 16.000s 90.155us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 14.000s 37.895us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 14.000s 37.895us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 12.000s 28.654us 5 7 71.43
V2S sec_cm_data_mem_sec_wipe otbn_single 34.000s 396.099us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 34.000s 396.099us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 34.000s 396.099us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.483m 684.628us 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 34.000s 396.099us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 34.000s 396.099us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 15.000s 52.802us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 34.000s 396.099us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.050m 1.537ms 2 5 40.00
V2S TOTAL 66 163 40.49
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 10.350m 3.036ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 293 585 50.09

Failure Buckets