6adf14f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 9.000s | 177.189us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 3.000s | 24.542us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 3.000s | 14.582us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 282.856us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 49.501us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 3.000s | 17.156us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 3.000s | 14.582us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 49.501us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 53.733m | 600.000ms | 26 | 50 | 52.00 |
| V2 | cnt_rollover | cnt_rollover | 1.233m | 5.368ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 3.000s | 64.623us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.956h | 2.745s | 18 | 50 | 36.00 |
| V2 | alert_test | pattgen_alert_test | 3.000s | 47.126us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 3.000s | 30.926us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 5.000s | 193.764us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 5.000s | 193.764us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 3.000s | 24.542us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 14.582us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 49.501us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 23.183us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 3.000s | 24.542us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 14.582us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 49.501us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 23.183us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 340 | 83.53 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 94.125us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 3.000s | 156.519us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 94.125us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 1.917m | 10.105ms | 2 | 50 | 4.00 |
| V3 | TOTAL | 2 | 50 | 4.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.233m | 10.005ms | 36 | 50 | 72.00 | |
| TOTAL | 452 | 570 | 79.30 |
UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:
0.pattgen_stress_all_with_rand_reset.69310235113622542235411053255331881073854861452318659870464435332025274409174
Line 241, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5709841202 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 5709855716 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5709855716 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 5710272386 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.91580745984878389060187640348172803740058629384956207504010163616529497399481
Line 263, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1738411251 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1738418379 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1738418379 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 1738518379 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 46 more failures.
Job timed out after * minutes has 32 failures:
1.pattgen_stress_all.48940749145272431892936859547449406404991871937336320293909535056998416588237
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
2.pattgen_stress_all.49512690323328111410016665568021875197144134249369936688312809458843506487502
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 16 more failures.
10.pattgen_perf.15926216390014637096476200114958008473657564759959576186833808333176960530875
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log
Job timed out after 60 minutes
13.pattgen_perf.100691270959208474951038076441897983483455967711263345859689582022684978553057
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 12 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 14 failures:
0.pattgen_stress_all.30286838643696810570029073363091714942745399291734044581746178419727327189068
Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 50656567 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10322
3.pattgen_stress_all.32569873948437879604198108747239390599449775512255035626196045962743501056406
Line 132, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
UVM_ERROR @ 60654166 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10406
... and 12 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
0.pattgen_perf.5084471224904936089062563277468632768697224042867124315018916018729295678580
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pattgen_perf.9373376545471807382667573159835942596652560144679617849579878678547402736383
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
10.pattgen_inactive_level.38853584907452072187317495657706661647666736247879616065457659616707005736711
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002407656 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8c782890, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002407656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.pattgen_inactive_level.94557517271650263480784560228432405604563380146715025415261022682365902078325
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009929415 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x704f8410, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10009929415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
18.pattgen_inactive_level.102770047863349974700212362394980111980524230416541176331334937332237687528587
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10021838207 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x69d8e350, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10021838207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.pattgen_inactive_level.42734678997026703096021727630128494319565067116720983173979364159315321620539
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10014432069 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5e6d6450, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10014432069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
43.pattgen_inactive_level.73695575968763211624661498025606611728165682553058806392619511951543798350612
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10495383302 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x61cc56d0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10495383302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.pattgen_inactive_level.64029773151244544363733114086629801326057573578915139968075841813381018354350
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004718753 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x182f4090, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004718753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
6.pattgen_inactive_level.89718484239566079393673981246607900757185749750836631350807689834417712435927
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10155201518 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x95130450, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10155201518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
17.pattgen_inactive_level.97002141674940825962204018517178765715979875076908689322369348177091075859082
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025987854 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfb195850, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10025987854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
22.pattgen_inactive_level.100366120681963311066840949089263725581577002196624374158568626496818850869887
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012937080 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5cc4b3d0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10012937080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
28.pattgen_inactive_level.100070156572144271164917005188645038858441547927680704716088934271934254615
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025654387 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe005e090, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10025654387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
31.pattgen_inactive_level.70856778284439042834794561243397606714024741940812270380828639437373925754288
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10079111016 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9cf84a90, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10079111016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
47.pattgen_inactive_level.86703903248459353651011193861338707237044625227416845084754236954905796857788
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004563148 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xf0815290, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10004563148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 1 failures:
cov_merge
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: