ROM_CTRL/32KB Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.270s	181.208us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.700s	172.096us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.000s	173.429us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.010s	126.073us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.250s	1.068ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.760s	2.988ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.000s	173.429us	20	20	100.00
		rom_ctrl_csr_aliasing	6.250s	1.068ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.560s	1.943ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.850s	557.542us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.900s	575.326us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	21.610s	417.333us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.200s	1.092ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.360s	5.529ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.190s	173.066us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.190s	173.066us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.700s	172.096us	5	5	100.00
		rom_ctrl_csr_rw	7.000s	173.429us	20	20	100.00
		rom_ctrl_csr_aliasing	6.250s	1.068ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.950s	169.530us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.700s	172.096us	5	5	100.00
		rom_ctrl_csr_rw	7.000s	173.429us	20	20	100.00
		rom_ctrl_csr_aliasing	6.250s	1.068ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.950s	169.530us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	26.260s	1.627ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.843m	948.924us	5	5	100.00
		rom_ctrl_tl_intg_err	1.027m	360.318us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.843m	948.924us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.843m	948.924us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.843m	948.924us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.843m	948.924us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.270s	181.208us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.270s	181.208us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.270s	181.208us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.027m	360.318us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
		rom_ctrl_kmac_err_chk	9.200s	1.092ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.010m	3.741ms	17	20	85.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	26.260s	1.627ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.843m	948.924us	5	5	100.00
V2S		TOTAL			62	65	95.38
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	8.299m	4.901ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			263	266	98.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.54	99.73	98.81	100.00	100.00	100.00	98.98	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.

    • 7.rom_ctrl_corrupt_sig_fatal_chk.91915764282258211636379632853778949109572650963860011213856005027011397303939
      Line 98, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 3037074587 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 3037074587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.rom_ctrl_corrupt_sig_fatal_chk.101588444583213917523971776489268817729908614208891198073113597827677596008143
      Line 102, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 6513415223 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 6513415223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.