RV_TIMER Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.880s	31.355us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.880s	19.411us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.890s	162.088us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.620s	548.270us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.870s	91.492us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.670s	34.304us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.890s	162.088us	20	20	100.00
		rv_timer_csr_aliasing	0.870s	91.492us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	13.960s	8.165ms	20	20	100.00
V2	disabled	rv_timer_disabled	3.140s	2.816ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	10.059m	1.618s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	10.059m	1.618s	10	10	100.00
V2	stress	rv_timer_stress_all	8.030s	9.310ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.860s	39.162us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.810s	14.565us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.070s	668.139us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.070s	668.139us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.880s	19.411us	5	5	100.00
		rv_timer_csr_rw	0.890s	162.088us	20	20	100.00
		rv_timer_csr_aliasing	0.870s	91.492us	5	5	100.00
		rv_timer_same_csr_outstanding	0.970s	18.516us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.880s	19.411us	5	5	100.00
		rv_timer_csr_rw	0.890s	162.088us	20	20	100.00
		rv_timer_csr_aliasing	0.870s	91.492us	5	5	100.00
		rv_timer_same_csr_outstanding	0.970s	18.516us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.220s	372.088us	5	5	100.00
		rv_timer_tl_intg_err	1.870s	6.813ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.870s	6.813ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	0.900s	197.511us	10	10	100.00
V3	max_value	rv_timer_max	0.890s	57.508us	10	10	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	50.210s	36.618ms	20	20	100.00
V3		TOTAL			40	40	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	100.00	100.00	78.66	--	100.00	100.00	100.00