SPI_DEVICE/1R1W Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.666m	238.850ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	25.411us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.760s	113.548us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.360s	2.779ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.600s	2.996ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.530s	123.291us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.760s	113.548us	20	20	100.00
		spi_device_csr_aliasing	11.600s	2.996ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.840s	98.411us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.170s	198.618us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.130s	18.723us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.030s	3.204us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.850s	3.921us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	8.210s	267.840us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.210s	267.840us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.840s	13.341ms	50	50	100.00
		spi_device_tpm_sts_read	1.320s	131.087us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.090s	33.250ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.800s	8.004ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	22.550s	29.962ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	22.550s	29.962ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	21.190s	3.991ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	21.190s	3.991ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	21.190s	3.991ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	21.190s	3.991ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	21.190s	3.991ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	28.260s	101.027ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.752m	70.428ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.752m	70.428ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.752m	70.428ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	45.960s	3.039ms	50	50	100.00
		spi_device_read_buffer_direct	21.110s	2.209ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.752m	70.428ms	50	50	100.00
		spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.132m	295.243ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.760s	13.254ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.760s	13.254ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.666m	238.850ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.973m	285.187ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.644m	227.509ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.110s	17.488us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.010s	45.028us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.490s	1.043ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.490s	1.043ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	25.411us	5	5	100.00
		spi_device_csr_rw	2.760s	113.548us	20	20	100.00
		spi_device_csr_aliasing	11.600s	2.996ms	5	5	100.00
		spi_device_same_csr_outstanding	4.380s	344.274us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	25.411us	5	5	100.00
		spi_device_csr_rw	2.760s	113.548us	20	20	100.00
		spi_device_csr_aliasing	11.600s	2.996ms	5	5	100.00
		spi_device_same_csr_outstanding	4.380s	344.274us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.640s	192.999us	5	5	100.00
		spi_device_tl_intg_err	18.080s	1.090ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.080s	1.090ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.868m	310.607ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.81	99.11	96.56	71.19	89.36	98.42	95.76	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.12243199419581612427498275986582019253075991093093807862615385866099011544309
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1149111 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[4])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1149111 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1149111 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[900])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.59976534051974200885409802200805882513356672906904810227328419273868164559975
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4629489 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[9])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4629489 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4629489 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.48638117238305960482920801515864454805680553885557335998941513401410585441093
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1242875 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdca14b [110111001010000101001011] vs 0x0 [0])
        UVM_ERROR @   1313875 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbd546a [101111010101010001101010] vs 0x0 [0])
        UVM_ERROR @   1367875 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x21b97d [1000011011100101111101] vs 0x0 [0])
        UVM_ERROR @   1368875 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa6fbc4 [101001101111101111000100] vs 0x0 [0])
        UVM_ERROR @   1447875 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd49d04 [110101001001110100000100] vs 0x0 [0])