SPI_DEVICE/2P Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.344m	157.699ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.320s	99.353us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.400s	84.876us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.770s	5.410ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.250s	1.438ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.450s	985.892us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.400s	84.876us	20	20	100.00
		spi_device_csr_aliasing	17.250s	1.438ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.910s	23.826us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.950s	72.861us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.160s	21.740us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.440s	34.540us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.060s	37.816us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.690s	126.303us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.690s	126.303us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.580s	8.394ms	50	50	100.00
		spi_device_tpm_sts_read	1.520s	136.867us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	37.550s	6.310ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	15.970s	43.120ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.370s	32.541ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.370s	32.541ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	32.620s	15.312ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	32.620s	15.312ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	32.620s	15.312ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	32.620s	15.312ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	32.620s	15.312ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.880s	9.451ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.527m	57.389ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.527m	57.389ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.527m	57.389ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.047m	17.072ms	50	50	100.00
		spi_device_read_buffer_direct	22.980s	1.830ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.527m	57.389ms	50	50	100.00
		spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.796m	159.910ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.930s	2.865ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.930s	2.865ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.344m	157.699ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.796m	189.704ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.680m	497.608ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.090s	67.244us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.990s	56.407us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.710s	983.846us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.710s	983.846us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.320s	99.353us	5	5	100.00
		spi_device_csr_rw	2.400s	84.876us	20	20	100.00
		spi_device_csr_aliasing	17.250s	1.438ms	5	5	100.00
		spi_device_same_csr_outstanding	3.960s	881.514us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.320s	99.353us	5	5	100.00
		spi_device_csr_rw	2.400s	84.876us	20	20	100.00
		spi_device_csr_aliasing	17.250s	1.438ms	5	5	100.00
		spi_device_same_csr_outstanding	3.960s	881.514us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.690s	88.716us	5	5	100.00
		spi_device_tl_intg_err	18.170s	4.180ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.170s	4.180ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.228m	247.745ms	49	50	98.00
		TOTAL			1150	1151	99.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.35	99.17	96.65	74.78	89.36	98.49	95.74	99.26

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 3.spi_device_flash_mode_ignore_cmds.113296976117632294250731196044688850638953096781176779364677523815237897051247
      Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job timed out after 60 minutes