SPI_HOST Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: `6adf14f`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.667m	14.479ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	50.642us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	18.259us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	823.423us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	24.394us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	123.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	18.259us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.394us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	17.263us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	33.862us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	35.000s	25.627us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	35.000s	63.581us	50	50	100.00
		spi_host_error_cmd	30.000s	17.437us	50	50	100.00
		spi_host_event	11.783m	88.857ms	50	50	100.00
V2	clock_rate	spi_host_speed	40.000s	397.984us	50	50	100.00
V2	speed	spi_host_speed	40.000s	397.984us	50	50	100.00
V2	chip_select_timing	spi_host_speed	40.000s	397.984us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.617m	8.711ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	28.000s	45.378us	50	50	100.00
V2	cpol_cpha	spi_host_speed	40.000s	397.984us	50	50	100.00
V2	full_cycle	spi_host_speed	40.000s	397.984us	50	50	100.00
V2	duplex	spi_host_smoke	2.667m	14.479ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.667m	14.479ms	50	50	100.00
V2	stress_all	spi_host_stress_all	4.300m	1.000s	49	50	98.00
V2	spien	spi_host_spien	2.733m	31.966ms	50	50	100.00
V2	stall	spi_host_status_stall	10.817m	106.821ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	59.000s	2.232ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	35.000s	63.581us	50	50	100.00
V2	alert_test	spi_host_alert_test	17.000s	17.511us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	42.383us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	109.515us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	109.515us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	50.642us	5	5	100.00
		spi_host_csr_rw	3.000s	18.259us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.394us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	18.649us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	50.642us	5	5	100.00
		spi_host_csr_rw	3.000s	18.259us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.394us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	18.649us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	357.353us	20	20	100.00
		spi_host_sec_cm	22.000s	184.314us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	357.353us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.183m	6.226ms	10	10	100.00
		TOTAL			838	840	99.76

Failure Buckets

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

20.spi_host_status_stall.4493859434188466572632656737161563345649147389324623168951246833544675575386
Line 4455, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 1991523520 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 1991523520 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=1991524000 ps
  UVM_INFO @ 1991523520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 34.spi_host_stress_all.13400909827738256848708165626718450090580740769327893171188777755197062914709
    Line 126, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/34.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test spi_host has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/spi_host-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test spi_host has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/spi_host-sim-xcelium/cov_report/cov_report.log