SRAM_CTRL/MAIN Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.926m	2.053ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	27.277us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.020s	18.750us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.760s	155.659us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.100s	19.582us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	36.890s	10.001ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.020s	18.750us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	19.582us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.130m	43.124ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.836m	10.198ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	19.542m	136.381ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.773m	18.053ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.745m	1.916s	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.549m	63.388ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.127m	79.869ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.219m	125.121ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.884m	3.402ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.240m	39.747ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.848m	1.559ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.041m	786.857us	50	50	100.00
		sram_ctrl_throughput_w_readback	2.035m	3.662ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.513m	74.763ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.220s	6.627ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.315h	1.942s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.040s	171.217us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.370s	592.162us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.370s	592.162us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	27.277us	5	5	100.00
		sram_ctrl_csr_rw	1.020s	18.750us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	19.582us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.180s	69.683us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	27.277us	5	5	100.00
		sram_ctrl_csr_rw	1.020s	18.750us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	19.582us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.180s	69.683us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	55.830s	28.109ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.860s	13.068us	0	5	0.00
		sram_ctrl_tl_intg_err	4.160s	783.512us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.860s	13.068us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.160s	783.512us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.513m	74.763ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.513m	74.763ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.020s	18.750us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.219m	125.121ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.219m	125.121ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.219m	125.121ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.127m	79.869ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	14.050s	13.164ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	55.830s	28.109ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.580s	7.321ms	43	50	86.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.926m	2.053ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.926m	2.053ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.219m	125.121ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.860s	13.068us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.127m	79.869ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.860s	13.068us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.860s	13.068us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.926m	2.053ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.860s	13.068us	0	5	0.00
V2S		TOTAL			127	145	87.59
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.545m	4.121ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1171	1190	98.40

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.09	99.11	92.90	85.46	100.00	98.02	98.61	98.52

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 7 failures:
  • Test sram_ctrl_readback_err has 7 failures.

    • 0.sram_ctrl_readback_err.114085047307861306574246438889502575243400466273264054081294939786772931644172
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2987742980 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x15) != exp (0x59)
        UVM_INFO @ 2987742980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_readback_err.79209137030589386817499010326446063635949837070001434050056375571165190627104
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 678101988 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x0) != exp (0x59)
        UVM_INFO @ 678101988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:
  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 0.sram_ctrl_mubi_enc_err.90838003089108273976066819138693071998467667564375030933586616333907508499637
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 660967545 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 660967545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_mubi_enc_err.102568923106937976731401484528377397507374888205687495060022334286347604969654
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 677621315 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 677621315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 5 failures:
  • Test sram_ctrl_sec_cm has 5 failures.

    • 0.sram_ctrl_sec_cm.13200870120334253627236846034832382112945051482668417445343046699570149533549
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6606268 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6606268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.35262770643685073769912987985864638071326759633668227063626675594404991110696
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5484798 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5484798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 2.sram_ctrl_csr_mem_rw_with_rand_reset.24170978580166630735124280086122733229313894100891678286942972282030340269623
      Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_FATAL @ 10001303775 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
        UVM_INFO @ 10001303775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---