SRAM_CTRL/RET Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: 6adf14f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.423m	2.676ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.990s	55.874us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.050s	17.995us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.340s	1.205ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.050s	22.941us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.190s	353.149us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.050s	17.995us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	22.941us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.500s	2.167ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.590s	322.151us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	31.671m	21.081ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.004m	8.152ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.639m	7.566ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.432m	52.160ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.340s	779.468us	50	50	100.00
V2	executable	sram_ctrl_executable	27.104m	53.635ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.788m	648.172us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.432m	45.926ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.711m	515.547us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.715m	150.032us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.872m	293.288us	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.423m	26.820ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.150s	56.181us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.176h	447.056ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.030s	25.669us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.150s	292.936us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.150s	292.936us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.990s	55.874us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	17.995us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	22.941us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.200s	235.775us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.990s	55.874us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	17.995us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	22.941us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.200s	235.775us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.720s	482.000us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.990s	8.583us	0	5	0.00
		sram_ctrl_tl_intg_err	3.350s	210.653us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.990s	8.583us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.350s	210.653us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.423m	26.820ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.423m	26.820ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.050s	17.995us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.104m	53.635ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.104m	53.635ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.104m	53.635ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.340s	779.468us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.460s	45.898us	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.720s	482.000us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.570s	35.313us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.423m	2.676ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.423m	2.676ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.104m	53.635ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.990s	8.583us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.340s	779.468us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.990s	8.583us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.990s	8.583us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.423m	2.676ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.990s	8.583us	0	5	0.00
V2S		TOTAL			126	145	86.90
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.697m	2.378ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1168	1190	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	99.07	92.90	85.37	100.00	97.98	98.60	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 2.sram_ctrl_readback_err.8574564371938259373178375983486586751513757761790171238181653134473945989477
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  48437480 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x41)
        UVM_INFO @  48437480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.108903269754491483403816939591737249954607145521572324529602083677094328274250
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  54102694 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1a) != exp (0x78)
        UVM_INFO @  54102694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.112628697316326351740846823321771232776301894898760725913659098831370865164379
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1757486 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1757486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.68044308524743042419938720245451914804623354827433146811415943836962865358937
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8583133 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8583133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending 'reqfifo_rvalid' has 4 failures:

  • Test sram_ctrl_mubi_enc_err has 4 failures.

    • 9.sram_ctrl_mubi_enc_err.23057590544689057501136739890128732600022917520915534953313013530502875831599
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  95649777 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  95649777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 16.sram_ctrl_mubi_enc_err.74201983650783352250858822896169427198868786670809624739939862461895129164968
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  37992229 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  37992229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.55754399130488225215848771002996078311120590118450523999444224687571268053454
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  45139518 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  45139518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 8.sram_ctrl_csr_mem_rw_with_rand_reset.90131539722291088676159463380844540567430008575511179811992423466745454074179
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  23568068 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
        UVM_INFO @  23568068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 9.sram_ctrl_csr_mem_rw_with_rand_reset.90120808608759866323010045587440941582271047589882895233193801503283473438466
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  23471096 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @  23471096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 17.sram_ctrl_csr_mem_rw_with_rand_reset.69937280393667263139683839946035582168662286888731044982853456489034904908755
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 227706608 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @ 227706608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---