SYSRST_CTRL Simulation Results

Sunday September 07 2025 00:10:53 UTC

GitHub Revision: `6adf14f`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	8.840s	2.106ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	11.170s	2.457ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.340s	2.416ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	4.210s	2.518ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	18.870s	6.029ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	8.490s	2.063ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.461m	38.859ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	11.530s	2.424ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	9.120s	2.086ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	8.490s	2.063ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.530s	2.424ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	6.929m	134.852ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.804m	174.719ms	92	100	92.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	10.257m	280.692ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	25.479m	1.536s	44	50	88.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	10.330s	2.510ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	9.070s	2.165ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	35.572m	916.815ms	49	50	98.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	10.380s	2.612ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	11.156m	2.329s	37	50	74.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.106m	33.942ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	18.105m	1.448s	47	50	94.00
V2	alert_test	sysrst_ctrl_alert_test	7.900s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	7.740s	2.013ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.660s	2.082ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.660s	2.082ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	18.870s	6.029ms	5	5	100.00
		sysrst_ctrl_csr_rw	8.490s	2.063ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.530s	2.424ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	33.430s	7.903ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	18.870s	6.029ms	5	5	100.00
		sysrst_ctrl_csr_rw	8.490s	2.063ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.530s	2.424ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	33.430s	7.903ms	20	20	100.00
V2		TOTAL			661	692	95.52
V2S	tl_intg_err	sysrst_ctrl_sec_cm	39.410s	42.046ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	2.361m	42.470ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	2.361m	42.470ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	21.510s	10.796ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			901	932	96.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.35	98.98	97.96	100.00	94.87	99.11	99.23	91.31

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 17 failures:

Test sysrst_ctrl_ultra_low_pwr has 9 failures.

0.sysrst_ctrl_ultra_low_pwr.54131772556777389872766927444662618781887595034813554365602531554919790940598
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3671571202 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 3671632425 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 3671632425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sysrst_ctrl_ultra_low_pwr.801377372758779414606237684896367693404770657454082552040307604631628898846
Line 383, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 5844944335 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 5845064334 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 5845064334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test sysrst_ctrl_stress_all has 2 failures.

10.sysrst_ctrl_stress_all.84648976381437618030426492197732943237055239838514236229184751772033391228235
Line 383, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 215973098864 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 215973241720 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 215973241720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.sysrst_ctrl_stress_all.111471798221611204090028370782599859168539254651269246064220102407356314051639
Line 423, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 439454081199 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 439454192309 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 439454192309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_edge_detect has 6 failures.

11.sysrst_ctrl_edge_detect.90846257390923987422268560412583474457393925076114428393098302906840304126167
Line 392, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 2715245246 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 2715306469 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 2715306469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sysrst_ctrl_edge_detect.28043114087768482407462664541082281076707307824952647319018656320964804253999
Line 386, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 2976024269 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 2976055195 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 2976055195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 4 failures:

Test sysrst_ctrl_ultra_low_pwr has 4 failures.

14.sysrst_ctrl_ultra_low_pwr.18329696027472149935801831629217164156160127100811498605598125649579611720004
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2286638168 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 352854138168 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 352854138168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sysrst_ctrl_ultra_low_pwr.80496822362233777104446887476513763243562256121305815489881618547898786416621
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 6890470820 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 9792970820 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9792970820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 4 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 4 failures.

32.sysrst_ctrl_combo_detect_with_pre_cond.39410351172644828964762832660029729382174664107372368102821884343063792102608
Line 417, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 33031749807 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 33031749807 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 33031749807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.sysrst_ctrl_combo_detect_with_pre_cond.22877939595947418451356444885246680236359551582708261790645563073151971989079
Line 434, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 85473560248 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 85473560248 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 85473560248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 2 failures:
- Test sysrst_ctrl_stress_all has 1 failures.
  - 29.sysrst_ctrl_stress_all.40581544220173964989722586519510602225947829698393502908400147469700332414414
    Line 394, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 16059875718 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 16059875718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 31.sysrst_ctrl_ec_pwr_on_rst.82490428791213917077064667327302095106094658776934835106709034407570428676373
    Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 4054086167 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 4054086167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

53.sysrst_ctrl_combo_detect_with_pre_cond.83017669610788014901506137393774240555826784874632473086633517381614189661406
Line 409, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 41009399337 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 41009399337 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 41009399337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

55.sysrst_ctrl_combo_detect_with_pre_cond.34202625795698013370684042251786369095349422329834764574277565546852231326366
Line 392, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13842399439 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 13842399439 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 13842399439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

0.sysrst_ctrl_combo_detect_with_pre_cond.56933400088552772184307905985986684800602922208930863904299358922707307156333
Line 389, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13171219324 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-4
  UVM_ERROR @ 13171219324 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4
  UVM_INFO @ 13171219324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

87.sysrst_ctrl_combo_detect_with_pre_cond.85104183917725065010255564288622057426311348212388253137655028926718990218204
Line 395, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 14642452026 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 24775831580 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x13
  UVM_INFO @ 24775954028 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1f
  UVM_INFO @ 25262452026 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
  UVM_INFO @ 25262452026 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1