ADC_CTRL Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: `e14e4d4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	20.760s	5.949ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.070s	1.251ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.550s	530.294us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.387m	26.483ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.420s	870.415us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.010s	532.269us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.550s	530.294us	20	20	100.00
		adc_ctrl_csr_aliasing	4.420s	870.415us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.150m	489.711ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.280m	492.194ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	17.954m	484.651ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	21.039m	499.413ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.617m	556.658ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	28.163m	614.054ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.040m	547.914ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	20.212m	571.681ms	34	50	68.00
V2	poweron_counter	adc_ctrl_poweron_counter	17.550s	5.138ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.220m	40.530ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	7.074m	131.237ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	59.184m	1.742s	48	50	96.00
V2	alert_test	adc_ctrl_alert_test	2.420s	529.641us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.500s	509.697us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.810s	585.211us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.810s	585.211us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.070s	1.251ms	5	5	100.00
		adc_ctrl_csr_rw	2.550s	530.294us	20	20	100.00
		adc_ctrl_csr_aliasing	4.420s	870.415us	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.660s	4.626ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.070s	1.251ms	5	5	100.00
		adc_ctrl_csr_rw	2.550s	530.294us	20	20	100.00
		adc_ctrl_csr_aliasing	4.420s	870.415us	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.660s	4.626ms	20	20	100.00
V2		TOTAL			718	740	97.03
V2S	tl_intg_err	adc_ctrl_sec_cm	20.090s	7.847ms	5	5	100.00
		adc_ctrl_tl_intg_err	16.670s	8.248ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	16.670s	8.248ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	44.987m	10.000s	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			895	920	97.28

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	99.05	96.03	100.00	100.00	98.64	95.95	90.98

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 14 failures:
- Test adc_ctrl_clock_gating has 11 failures.
  - 9.adc_ctrl_clock_gating.106559803057892422792348568267015700644454342929276549350711244922660096102568
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.adc_ctrl_clock_gating.41920306547342894675673226519768406214331278927305630615602941530507134980133
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.adc_ctrl_stress_all_with_rand_reset.58912740240755006663633238356217536170606493147649963650818536523737306509897
    Line 161, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all has 2 failures.
  - 24.adc_ctrl_stress_all.96013915558544393483874320009289650659845426924566619476667314239526282529107
    Line 159, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.adc_ctrl_stress_all.35970283297625160519339309600029389708511843765033713068911391224204970663527
    Line 149, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 5 failures:
- Test adc_ctrl_clock_gating has 5 failures.
  - 8.adc_ctrl_clock_gating.29441391670248379114453259895268955889714434165669269968862575421859265898498
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 172575240436 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 172575240436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.adc_ctrl_clock_gating.67235260691497257687040372234653837674405259626377933727916256413603474846959
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 161752828688 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 161752828688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_filters_both has 3 failures.

3.adc_ctrl_filters_both.22025726400399844792983357414786031245197869502538199018117339145623376643908
Line 164, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 327727189774 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 327727189774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.adc_ctrl_filters_both.52533162642101418159596693454500162976873100068200419078675039619944977089307
Line 164, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 325582236235 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 325582236235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_filters_interrupt has 1 failures.

28.adc_ctrl_filters_interrupt.105874000149264170223368467057717104989403416414467308081333510787848490675075
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 81217091016 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 81217091016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:849) [adc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 10.adc_ctrl_stress_all_with_rand_reset.22613397901813616549341890916857670898539208107423101497209166849866968452873
    Line 199, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18849809561 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 18849809561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.adc_ctrl_stress_all_with_rand_reset.74291939599626944152028315080913283779157219082579025093055583802390672439696
    Line 190, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7505756727 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7505756727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```