AES/MASKED Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: `e14e4d4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	95.819us	1	1	100.00
V1	smoke	aes_smoke	8.000s	134.826us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	60.028us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	245.115us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	645.187us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	233.015us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	145.001us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	245.115us	20	20	100.00
		aes_csr_aliasing	5.000s	233.015us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	134.826us	50	50	100.00
		aes_config_error	21.000s	1.604ms	50	50	100.00
		aes_stress	1.083m	3.156ms	50	50	100.00
V2	key_length	aes_smoke	8.000s	134.826us	50	50	100.00
		aes_config_error	21.000s	1.604ms	50	50	100.00
		aes_stress	1.083m	3.156ms	50	50	100.00
V2	back2back	aes_stress	1.083m	3.156ms	50	50	100.00
		aes_b2b	35.000s	595.801us	50	50	100.00
V2	backpressure	aes_stress	1.083m	3.156ms	50	50	100.00
V2	multi_message	aes_smoke	8.000s	134.826us	50	50	100.00
		aes_config_error	21.000s	1.604ms	50	50	100.00
		aes_stress	1.083m	3.156ms	50	50	100.00
		aes_alert_reset	19.000s	969.486us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	311.344us	50	50	100.00
		aes_config_error	21.000s	1.604ms	50	50	100.00
		aes_alert_reset	19.000s	969.486us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.783m	8.274ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	445.070us	1	1	100.00
V2	reset_recovery	aes_alert_reset	19.000s	969.486us	50	50	100.00
V2	stress	aes_stress	1.083m	3.156ms	50	50	100.00
V2	sideload	aes_stress	1.083m	3.156ms	50	50	100.00
		aes_sideload	45.000s	1.848ms	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	280.821us	50	50	100.00
V2	stress_all	aes_stress_all	45.000s	2.695ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	86.332us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	263.453us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	263.453us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	60.028us	5	5	100.00
		aes_csr_rw	4.000s	245.115us	20	20	100.00
		aes_csr_aliasing	5.000s	233.015us	5	5	100.00
		aes_same_csr_outstanding	4.000s	84.771us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	60.028us	5	5	100.00
		aes_csr_rw	4.000s	245.115us	20	20	100.00
		aes_csr_aliasing	5.000s	233.015us	5	5	100.00
		aes_same_csr_outstanding	4.000s	84.771us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	26.000s	1.239ms	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_cipher_fi	58.000s	10.003ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	99.936us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	99.936us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	99.936us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	99.936us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	215.085us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	530.750us	5	5	100.00
		aes_tl_intg_err	5.000s	598.067us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	598.067us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	19.000s	969.486us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	99.936us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	134.826us	50	50	100.00
		aes_stress	1.083m	3.156ms	50	50	100.00
		aes_alert_reset	19.000s	969.486us	50	50	100.00
		aes_core_fi	1.767m	7.396ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	99.936us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	255.325us	50	50	100.00
		aes_stress	1.083m	3.156ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.083m	3.156ms	50	50	100.00
		aes_sideload	45.000s	1.848ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	255.325us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	255.325us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	255.325us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	255.325us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	255.325us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.083m	3.156ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.083m	3.156ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	603.189us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_cipher_fi	58.000s	10.003ms	337	350	96.29
		aes_ctr_fi	4.000s	87.171us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	603.189us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_cipher_fi	58.000s	10.003ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	58.000s	10.003ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	603.189us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_ctr_fi	4.000s	87.171us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_cipher_fi	58.000s	10.003ms	337	350	96.29
		aes_ctr_fi	4.000s	87.171us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	19.000s	969.486us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_cipher_fi	58.000s	10.003ms	337	350	96.29
		aes_ctr_fi	4.000s	87.171us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_cipher_fi	58.000s	10.003ms	337	350	96.29
		aes_ctr_fi	4.000s	87.171us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_ctr_fi	4.000s	87.171us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	603.189us	48	50	96.00
		aes_control_fi	59.000s	10.003ms	278	300	92.67
		aes_cipher_fi	58.000s	10.003ms	337	350	96.29
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	36.000s	2.228ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_control_fi has 15 failures.
  - 10.aes_control_fi.28324878225155596699449621685006675893769711846331760787865271375423246682647
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 11.aes_control_fi.108117940159801037065538999304362179520906748937599569521642023683220630422417
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 37.aes_cipher_fi.31730445490366184174946237492916579017519700411773729538271677097618783334739
    Line 147, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014027135 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014027135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 40.aes_cipher_fi.99190037452871010862762047665637268678639356544317710120702637684259967861742
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016868972 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016868972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 1.aes_control_fi.57559970535651852938351776340200462853799511279130144206612787498098381465330
    Line 134, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020997465 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020997465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.aes_control_fi.44393720300139173110422769469602622748875273021175372914440555804657306840867
    Line 134, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021511559 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021511559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.22179071470988463154293512241263804439602795623548955604786908963480020972439
Line 323, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  73062025 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  73062025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.14637360170651193431260593372649724450489277102615670633571647443053938671336
Line 292, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  90952493 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  90952493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 4 failures:
- Test aes_stress_all_with_rand_reset has 4 failures.
  - 1.aes_stress_all_with_rand_reset.4686437825396136551574772537424422104456553584841321279347292549337238981126
    Line 156, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  51889085 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  51889085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_stress_all_with_rand_reset.61813337420008047033725861635665823320326083146741590580883247387832179270537
    Line 167, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  99578787 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  99578787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 8.aes_core_fi.38975020947316350650262529778776063432787111175989111122319789202381197064256
    Line 147, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012221587 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012221587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.aes_core_fi.92889572509426772004905854185163720750896998134204349891206287707766316944723
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010639618 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010639618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

4.aes_fi.68288417934566361927771960240347582680390509482868867643351587707512350128642
Line 30751, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_fi/latest/run.log

  UVM_FATAL @ 146251947 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 146251947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_fi.94333783697751398628602021195629362720360673245022992863197572070863859661787
Line 35744, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_fi/latest/run.log

  UVM_FATAL @ 603189327 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 603189327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:946) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.12349144693177832803767791654863354482044476727456218278190224520793483270903
    Line 161, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 226811824 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 226811824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,865): Assertion AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

51.aes_core_fi.2184531783370711686028317928414402324411004519152594908272123352927816707394
Line 131, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/51.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 5773671 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 5763362 PS)
  UVM_ERROR @   5773671 ps: (aes_cipher_core.sv:865) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateKeyExpand
  UVM_INFO @   5773671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.log