AES/UNMASKED Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: `e14e4d4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	127.263us	1	1	100.00
V1	smoke	aes_smoke	4.000s	112.775us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	76.124us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	75.054us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	194.220us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	339.685us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	173.525us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	75.054us	20	20	100.00
		aes_csr_aliasing	4.000s	339.685us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	112.775us	50	50	100.00
		aes_config_error	5.000s	64.543us	50	50	100.00
		aes_stress	5.000s	371.487us	50	50	100.00
V2	key_length	aes_smoke	4.000s	112.775us	50	50	100.00
		aes_config_error	5.000s	64.543us	50	50	100.00
		aes_stress	5.000s	371.487us	50	50	100.00
V2	back2back	aes_stress	5.000s	371.487us	50	50	100.00
		aes_b2b	11.000s	867.582us	50	50	100.00
V2	backpressure	aes_stress	5.000s	371.487us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	112.775us	50	50	100.00
		aes_config_error	5.000s	64.543us	50	50	100.00
		aes_stress	5.000s	371.487us	50	50	100.00
		aes_alert_reset	5.000s	82.081us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	65.497us	50	50	100.00
		aes_config_error	5.000s	64.543us	50	50	100.00
		aes_alert_reset	5.000s	82.081us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	217.156us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	186.149us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	82.081us	50	50	100.00
V2	stress	aes_stress	5.000s	371.487us	50	50	100.00
V2	sideload	aes_stress	5.000s	371.487us	50	50	100.00
		aes_sideload	5.000s	96.063us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	102.204us	50	50	100.00
V2	stress_all	aes_stress_all	27.000s	566.597us	9	10	90.00
V2	alert_test	aes_alert_test	4.000s	294.116us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	35.000s	185.590us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	35.000s	185.590us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	76.124us	5	5	100.00
		aes_csr_rw	4.000s	75.054us	20	20	100.00
		aes_csr_aliasing	4.000s	339.685us	5	5	100.00
		aes_same_csr_outstanding	4.000s	270.853us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	76.124us	5	5	100.00
		aes_csr_rw	4.000s	75.054us	20	20	100.00
		aes_csr_aliasing	4.000s	339.685us	5	5	100.00
		aes_same_csr_outstanding	4.000s	270.853us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	5.000s	231.627us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	36.000s	10.003ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	404.529us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	404.529us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	404.529us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	404.529us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	1.625ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	2.802ms	5	5	100.00
		aes_tl_intg_err	5.000s	580.133us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	580.133us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	82.081us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	404.529us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	112.775us	50	50	100.00
		aes_stress	5.000s	371.487us	50	50	100.00
		aes_alert_reset	5.000s	82.081us	50	50	100.00
		aes_core_fi	4.733m	10.012ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	404.529us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	54.872us	50	50	100.00
		aes_stress	5.000s	371.487us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	371.487us	50	50	100.00
		aes_sideload	5.000s	96.063us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	54.872us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	54.872us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	54.872us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	54.872us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	54.872us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	371.487us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	371.487us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	99.413us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	36.000s	10.003ms	322	350	92.00
		aes_ctr_fi	4.000s	60.517us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	99.413us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	36.000s	10.003ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	36.000s	10.003ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	99.413us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_ctr_fi	4.000s	60.517us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	36.000s	10.003ms	322	350	92.00
		aes_ctr_fi	4.000s	60.517us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	82.081us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	36.000s	10.003ms	322	350	92.00
		aes_ctr_fi	4.000s	60.517us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	36.000s	10.003ms	322	350	92.00
		aes_ctr_fi	4.000s	60.517us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_ctr_fi	4.000s	60.517us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	99.413us	50	50	100.00
		aes_control_fi	43.000s	10.004ms	282	300	94.00
		aes_cipher_fi	36.000s	10.003ms	322	350	92.00
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	29.000s	2.306ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Failure Buckets

Job timed out after * minutes has 32 failures:
- Test aes_ctr_fi has 1 failures.
  - 14.aes_ctr_fi.33476228550613905765651020596062499067800345476368475743488733782300429130623
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/14.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_cipher_fi has 17 failures.
  - 15.aes_cipher_fi.40218998718492691028861928887137232563689790201545966574792480984215957550546
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 60.aes_cipher_fi.12500671809639777371185452149716160453948905305873643831295495460255438018943
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 15 more failures.
- Test aes_control_fi has 14 failures.
  - 20.aes_control_fi.22336975901684559987785870242815168439495025745846860287631692077903426783248
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 28.aes_control_fi.56360487678171155930129758358885091449970603686969582981858613227477855760914
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 7.aes_cipher_fi.89855885770622817231001960483343674775673561665854387903570202086122174572078
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004727732 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004727732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 92.aes_cipher_fi.82801301966297426682635233832740659212199768428155549762940158084077212613998
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/92.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014236262 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014236262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.36741409129345025575749518782359582921873653760163084343820092604425856808809
Line 1336, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2305979797 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2305979797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.13036677093701462220582731898355705516759733387173867214003210564460961828940
Line 219, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 793024846 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 793024846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 58.aes_control_fi.51135276666564695874823568230230789560919888842364976661148675700799077631226
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10023495683 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023495683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 97.aes_control_fi.107771671092522461008555264240576843891616756825075062087564423793615072702981
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/97.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005394685 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005394685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 3 failures:

Test aes_core_fi has 3 failures.

37.aes_core_fi.5613426180489883164020423058182419955444479602977701461067004418104271952194
Line 144, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/37.aes_core_fi/latest/run.log

  UVM_FATAL @ 10012156549 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xdf198784, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10012156549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.aes_core_fi.109242338902310404525257734432188807271065108021295988117305821694029506069537
Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/48.aes_core_fi/latest/run.log

  UVM_FATAL @ 10018990589 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x9bcb8a84, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10018990589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

0.aes_stress_all.48118776022971204294706633743431199025343390547315611438410345731359188720835
Line 20404, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 1473903267 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 1473863267 PS)
  UVM_ERROR @ 1473903267 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 1473903267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.35501915821313758605068246504496254472808848610635946264614345436351505100273
    Line 347, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1251161982 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1251161982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 1 failures:
- Test aes_clear has 1 failures.
  - 4.aes_clear.94349120355613749583607319078271129124029391338869415635723686488411187696652
    Line 10069, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_clear/latest/run.log
```
  UVM_FATAL @ 152355675 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
       ----| Expected:           5
       ----| Seen:               6
       ----| Expected corrupted: 0
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.105820712407575993233081907313403935693222171167932552759882741436937594663073
    Line 155, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  16048385 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  16048385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 43.aes_core_fi.6351411419447105365056948345988551954627604581209156190138761080624951689222
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10032483874 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032483874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 47.aes_core_fi.31526489621290886553119185774566674425431511288392810082583013228239431048807
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007981710 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007981710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_report/cov_report.log