AON_TIMER Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.310s	545.234us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.940s	1.324ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.770s	426.037us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	17.590s	14.025ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.380s	499.734us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.060s	479.692us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.770s	426.037us	20	20	100.00
		aon_timer_csr_aliasing	1.380s	499.734us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.510s	513.340us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.780s	487.669us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	1.653m	60.714ms	15	15	100.00
V2	jump	aon_timer_jump	2.260s	730.610us	5	5	100.00
V2	stress_all	aon_timer_stress_all	1.957m	163.368ms	15	15	100.00
V2	alert_test	aon_timer_alert_test	2.070s	477.223us	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.960s	454.462us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.050s	458.567us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.050s	458.567us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.940s	1.324ms	5	5	100.00
		aon_timer_csr_rw	1.770s	426.037us	20	20	100.00
		aon_timer_csr_aliasing	1.380s	499.734us	5	5	100.00
		aon_timer_same_csr_outstanding	6.490s	3.042ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.940s	1.324ms	5	5	100.00
		aon_timer_csr_rw	1.770s	426.037us	20	20	100.00
		aon_timer_csr_aliasing	1.380s	499.734us	5	5	100.00
		aon_timer_same_csr_outstanding	6.490s	3.042ms	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	11.340s	7.914ms	5	5	100.00
		aon_timer_tl_intg_err	12.680s	8.431ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.680s	8.431ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	max_threshold	aon_timer_smoke_max_thold	2.370s	738.360us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	2.110s	690.566us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	10.780s	3.380ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	2.150s	553.221us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	17.350s	4.056ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	47.780s	62.363ms	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			315	315	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.89	99.09	99.05	100.00	--	98.56	96.67	100.00