CSRNG Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	227.402us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	46.655us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	128.025us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	28.000s	1.052ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	322.855us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	294.276us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	128.025us	20	20	100.00
		csrng_csr_aliasing	8.000s	322.855us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	25.000s	1.447ms	179	200	89.50
V2	alerts	csrng_alert	1.317m	5.747ms	500	500	100.00
V2	err	csrng_err	5.000s	21.650us	473	500	94.60
V2	cmds	csrng_cmds	6.450m	11.347ms	50	50	100.00
V2	life cycle	csrng_cmds	6.450m	11.347ms	50	50	100.00
V2	stress_all	csrng_stress_all	39.117m	167.771ms	50	50	100.00
V2	intr_test	csrng_intr_test	4.000s	31.228us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	45.560us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.605ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.605ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	46.655us	5	5	100.00
		csrng_csr_rw	5.000s	128.025us	20	20	100.00
		csrng_csr_aliasing	8.000s	322.855us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	299.610us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	46.655us	5	5	100.00
		csrng_csr_rw	5.000s	128.025us	20	20	100.00
		csrng_csr_aliasing	8.000s	322.855us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	299.610us	20	20	100.00
V2		TOTAL			1392	1440	96.67
V2S	tl_intg_err	csrng_sec_cm	13.000s	822.342us	5	5	100.00
		csrng_tl_intg_err	12.000s	233.665us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	106.290us	50	50	100.00
		csrng_csr_rw	5.000s	128.025us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.317m	5.747ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	39.117m	167.771ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.317m	5.747ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	39.117m	167.771ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.317m	5.747ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	233.665us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
		csrng_sec_cm	13.000s	822.342us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	25.000s	1.447ms	179	200	89.50
		csrng_err	5.000s	21.650us	473	500	94.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	9.217m	18.323ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1582	1630	97.06

Failure Buckets

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 18 failures:

  • Test csrng_err has 18 failures.

    • 59.csrng_err.105903622806424964970773476901165970119175527269921114158531414726512300142593
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/59.csrng_err/latest/run.log

        UVM_FATAL @   2873500 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   2873500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 122.csrng_err.4390238990029090894886921852529671286665607187042991335886619305727073669924
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/122.csrng_err/latest/run.log

        UVM_FATAL @   3067491 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   3067491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 16 more failures.

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 10 failures:

  • Test csrng_intr has 10 failures.

    • 11.csrng_intr.60629702385553909051047849432865027698026961024785405665810925954123300097378
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/11.csrng_intr/latest/run.log

        UVM_FATAL @  69104500 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @  69104500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 84.csrng_intr.101324872497537643728424343716724822699088072265376795433042519004265382833061
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/84.csrng_intr/latest/run.log

        UVM_FATAL @ 100211111 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 100211111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_err_vseq] has 9 failures:

  • Test csrng_err has 9 failures.

    • 5.csrng_err.27911853021219973798063892341245005386230714051245738603326367232121568120981
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/5.csrng_err/latest/run.log

        UVM_FATAL @   7715176 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   7715176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.csrng_err.38744442541175950658165794930701079011775143696431188298173121235933946067789
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/9.csrng_err/latest/run.log

        UVM_FATAL @   7563869 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   7563869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_intr_vseq] has 9 failures:

  • Test csrng_intr has 9 failures.

    • 20.csrng_intr.91524752023995165300205103240014242293707694075662767393344890270899931726310
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/20.csrng_intr/latest/run.log

        UVM_FATAL @ 262477493 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 262477493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 31.csrng_intr.2742599703886536409654556696905638024314194035829045198617543487690062047936
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/31.csrng_intr/latest/run.log

        UVM_FATAL @  38373057 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @  38373057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,514): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

  • Test csrng_intr has 2 failures.

    • 21.csrng_intr.111594802386620185001338128389905582338215293057046264184695240449507465958660
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/21.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,514): (time 295455616 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
        UVM_ERROR @ 295455616 ps: (csrng_cmd_stage.sv:514) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
        UVM_INFO @ 295455616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 147.csrng_intr.18487502872639233353314303213486240948470934250485590622073358251380838259511
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/147.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,514): (time 150629577 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
        UVM_ERROR @ 150629577 ps: (csrng_cmd_stage.sv:514) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
        UVM_INFO @ 150629577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test csrng has 1 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_merge/merged/cov_merge.log

        [Executing]:
        make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
      
        [make]: cov_merge
        imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
        *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
        Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
        Created log file /nightly/current_run/opentitan/startup.log
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
      

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test csrng has 1 failures.
    • cov_report
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.log