EDN Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.460s	22.292us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.190s	16.435us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.270s	16.988us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.010s	699.092us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.540s	44.012us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.870s	116.760us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.270s	16.988us	20	20	100.00
		edn_csr_aliasing	1.540s	44.012us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	6.360s	975.109us	300	300	100.00
V2	csrng_commands	edn_genbits	6.360s	975.109us	300	300	100.00
V2	genbits	edn_genbits	6.360s	975.109us	300	300	100.00
V2	interrupts	edn_intr	1.570s	20.848us	50	50	100.00
V2	alerts	edn_alert	1.940s	370.384us	200	200	100.00
V2	errs	edn_err	1.710s	36.279us	100	100	100.00
V2	disable	edn_disable	1.300s	19.222us	50	50	100.00
		edn_disable_auto_req_mode	2.200s	61.959us	50	50	100.00
V2	stress_all	edn_stress_all	8.030s	389.873us	50	50	100.00
V2	intr_test	edn_intr_test	1.210s	13.624us	50	50	100.00
V2	alert_test	edn_alert_test	1.480s	40.314us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.210s	141.610us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.210s	141.610us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.190s	16.435us	5	5	100.00
		edn_csr_rw	1.270s	16.988us	20	20	100.00
		edn_csr_aliasing	1.540s	44.012us	5	5	100.00
		edn_same_csr_outstanding	1.710s	120.654us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.190s	16.435us	5	5	100.00
		edn_csr_rw	1.270s	16.988us	20	20	100.00
		edn_csr_aliasing	1.540s	44.012us	5	5	100.00
		edn_same_csr_outstanding	1.710s	120.654us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	7.320s	967.409us	5	5	100.00
		edn_tl_intg_err	6.300s	552.981us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.260s	28.961us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.940s	370.384us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.320s	967.409us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.320s	967.409us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.320s	967.409us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.320s	967.409us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.940s	370.384us	200	200	100.00
		edn_sec_cm	7.320s	967.409us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.940s	370.384us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	6.300s	552.981us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.256h	10.000s	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1113	1130	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.49	98.87	94.23	97.02	91.28	96.33	97.56	93.13

Failure Buckets

• Job timed out after * minutes has 16 failures:
  • Test edn_stress_all_with_rand_reset has 16 failures.

    • 6.edn_stress_all_with_rand_reset.91072680621724973610083678587607984858951033399315601282068162262643157086977
      Log /nightly/current_run/scratch/master/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 7.edn_stress_all_with_rand_reset.73680551011730558137635944263343004625462130578869066548311192933236127281863
      Log /nightly/current_run/scratch/master/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 14 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 12.edn_stress_all_with_rand_reset.36538956161534099183447256581413265987338919135558151440859097026713979203894
      Line 403, in log /nightly/current_run/scratch/master/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---