HMAC Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.670s	9.959ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.310s	42.199us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.280s	134.005us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.660s	22.558ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.960s	552.123us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.132m	86.770ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.280s	134.005us	20	20	100.00
		hmac_csr_aliasing	7.960s	552.123us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.296m	25.358ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.864m	1.791ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.483m	30.616ms	30	30	100.00
		hmac_test_sha384_vectors	9.220m	15.046ms	75	75	100.00
		hmac_test_sha512_vectors	9.776m	12.209ms	75	75	100.00
		hmac_test_hmac256_vectors	15.660s	1.367ms	50	50	100.00
		hmac_test_hmac384_vectors	17.770s	437.497us	60	60	100.00
		hmac_test_hmac512_vectors	21.020s	435.787us	75	75	100.00
V2	burst_wr	hmac_burst_wr	40.960s	4.247ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.199m	8.500ms	10	10	100.00
V2	error	hmac_error	1.405m	6.023ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.898m	10.301ms	10	10	100.00
V2	save_and_restore	hmac_smoke	13.670s	9.959ms	10	10	100.00
		hmac_long_msg	1.296m	25.358ms	10	10	100.00
		hmac_back_pressure	1.864m	1.791ms	25	25	100.00
		hmac_datapath_stress	26.199m	8.500ms	10	10	100.00
		hmac_burst_wr	40.960s	4.247ms	50	50	100.00
		hmac_stress_all	35.798m	14.023ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.670s	9.959ms	10	10	100.00
		hmac_long_msg	1.296m	25.358ms	10	10	100.00
		hmac_back_pressure	1.864m	1.791ms	25	25	100.00
		hmac_datapath_stress	26.199m	8.500ms	10	10	100.00
		hmac_wipe_secret	1.898m	10.301ms	10	10	100.00
		hmac_test_sha256_vectors	4.483m	30.616ms	30	30	100.00
		hmac_test_sha384_vectors	9.220m	15.046ms	75	75	100.00
		hmac_test_sha512_vectors	9.776m	12.209ms	75	75	100.00
		hmac_test_hmac256_vectors	15.660s	1.367ms	50	50	100.00
		hmac_test_hmac384_vectors	17.770s	437.497us	60	60	100.00
		hmac_test_hmac512_vectors	21.020s	435.787us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.670s	9.959ms	10	10	100.00
		hmac_long_msg	1.296m	25.358ms	10	10	100.00
		hmac_back_pressure	1.864m	1.791ms	25	25	100.00
		hmac_datapath_stress	26.199m	8.500ms	10	10	100.00
		hmac_burst_wr	40.960s	4.247ms	50	50	100.00
		hmac_error	1.405m	6.023ms	10	10	100.00
		hmac_wipe_secret	1.898m	10.301ms	10	10	100.00
		hmac_test_sha256_vectors	4.483m	30.616ms	30	30	100.00
		hmac_test_sha384_vectors	9.220m	15.046ms	75	75	100.00
		hmac_test_sha512_vectors	9.776m	12.209ms	75	75	100.00
		hmac_test_hmac256_vectors	15.660s	1.367ms	50	50	100.00
		hmac_test_hmac384_vectors	17.770s	437.497us	60	60	100.00
		hmac_test_hmac512_vectors	21.020s	435.787us	75	75	100.00
		hmac_stress_all	35.798m	14.023ms	50	50	100.00
V2	stress_all	hmac_stress_all	35.798m	14.023ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.900s	13.618us	50	50	100.00
V2	intr_test	hmac_intr_test	0.920s	30.389us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.410s	2.067ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.410s	2.067ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.310s	42.199us	5	5	100.00
		hmac_csr_rw	1.280s	134.005us	20	20	100.00
		hmac_csr_aliasing	7.960s	552.123us	5	5	100.00
		hmac_same_csr_outstanding	2.510s	227.331us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.310s	42.199us	5	5	100.00
		hmac_csr_rw	1.280s	134.005us	20	20	100.00
		hmac_csr_aliasing	7.960s	552.123us	5	5	100.00
		hmac_same_csr_outstanding	2.510s	227.331us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.510s	117.212us	5	5	100.00
		hmac_tl_intg_err	5.320s	2.818ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.320s	2.818ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.670s	9.959ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.020s	452.830us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	17.389m	250.487ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	0.990s	20.391us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.63	99.95	96.74	100.00	100.00	99.83	97.61	47.30