I2C Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: `e14e4d4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.486m	2.051ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	44.760s	6.045ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.020s	19.382us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.000s	28.985us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.360s	2.602ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.080s	777.262us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.490s	486.436us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.000s	28.985us	20	20	100.00
		i2c_csr_aliasing	2.080s	777.262us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	11.948m	600.000ms	0	50	0.00
V2	host_stress_all	i2c_host_stress_all	41.724m	27.331ms	8	50	16.00
V2	host_maxperf	i2c_host_perf	24.756m	48.082ms	49	50	98.00
V2	host_override	i2c_host_override	1.040s	85.077us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.107m	51.904ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.179m	10.734ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.810s	245.068us	50	50	100.00
		i2c_host_fifo_fmt_empty	19.890s	5.522ms	50	50	100.00
		i2c_host_fifo_reset_rx	11.130s	220.097us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.811m	14.499ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	42.020s	1.772ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	6.560s	665.752us	12	50	24.00
V2	target_glitch	i2c_target_glitch	3.390s	640.503us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	22.975m	59.249ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	8.160s	2.476ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	59.200s	1.435ms	50	50	100.00
		i2c_target_intr_smoke	8.560s	4.406ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.410s	306.025us	50	50	100.00
		i2c_target_fifo_reset_tx	1.880s	729.763us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	17.507m	60.491ms	50	50	100.00
		i2c_target_stress_rd	59.200s	1.435ms	50	50	100.00
		i2c_target_intr_stress_wr	5.875m	23.849ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.830s	3.133ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.446m	4.917ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	8.100s	1.514ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	38.470s	10.150ms	26	50	52.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.290s	2.591ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.220s	196.713us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	24.756m	48.082ms	49	50	98.00
		i2c_host_perf_precise	8.589m	23.251ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	42.020s	1.772ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	25.220s	1.416ms	44	50	88.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.180s	5.245ms	50	50	100.00
		i2c_target_nack_acqfull_addr	3.800s	2.088ms	50	50	100.00
		i2c_target_nack_txstretch	2.350s	226.300us	34	50	68.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	23.530s	4.088ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.420s	546.849us	50	50	100.00
V2	alert_test	i2c_alert_test	0.960s	132.407us	50	50	100.00
V2	intr_test	i2c_intr_test	1.020s	77.768us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.600s	159.546us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.600s	159.546us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.020s	19.382us	5	5	100.00
		i2c_csr_rw	1.000s	28.985us	20	20	100.00
		i2c_csr_aliasing	2.080s	777.262us	5	5	100.00
		i2c_same_csr_outstanding	1.520s	94.661us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.020s	19.382us	5	5	100.00
		i2c_csr_rw	1.000s	28.985us	20	20	100.00
		i2c_csr_aliasing	2.080s	777.262us	5	5	100.00
		i2c_same_csr_outstanding	1.520s	94.661us	19	20	95.00
V2		TOTAL			1607	1792	89.68
V2S	tl_intg_err	i2c_tl_intg_err	2.790s	577.217us	20	20	100.00
		i2c_sec_cm	1.400s	337.266us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.790s	577.217us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	30.770s	861.927us	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.940s	628.517us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	16.350s	874.122us	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1787	2042	87.51

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.69	97.13	88.39	74.17	46.43	93.54	96.41	89.75

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 96 failures:

Test i2c_host_error_intr has 49 failures.

0.i2c_host_error_intr.41242764357868902430518542026752661919521100470682097750224556245800877901158
Line 96, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  25051874 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  25051874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.110325967077507593800438317811043715532811724811706454173699657792119981618228
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  60800470 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  60800470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 47 more failures.

Test i2c_host_stress_all has 31 failures.

0.i2c_host_stress_all.66523998296617920512776633201131442618194022805591356596559308568610578984691
Line 136, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 15949316092 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 15949316092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all.111072913619942114385597233498506358170790723096693170888185452277415067908847
Line 123, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 14702912559 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 14702912559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 29 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.

1.i2c_target_stress_all_with_rand_reset.85547034168996057681035224945357216240290402823827956299765892496395173634963
Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   8909839 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @   8909839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.58952650362582899337948760598256647398420245280316308789155667727248905892709
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 212524956 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 212524956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test i2c_host_mode_toggle has 11 failures.

3.i2c_host_mode_toggle.69387634665632175602006823768893255166222704142247020850898147628801598471947
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  26734653 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  26734653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_host_mode_toggle.21703247553974808626971400011488821519625878911256043742613875989613633090251
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  14452988 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  14452988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 28 failures:
- Test i2c_target_unexp_stop has 28 failures.
  - 0.i2c_target_unexp_stop.46237945921469092787161738033476797519729326746162086668792452092426109462673
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 102919726 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 254 [0xfe])
  UVM_INFO @ 102919726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.66008223199954578043664186042605582588736876363725363113849413794527796201036
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  36501185 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 157 [0x9d])
  UVM_INFO @  36501185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 26 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
- Test i2c_target_hrst has 24 failures.
  - 0.i2c_target_hrst.37602560507152821155152960738271288139573956748633532343996090081019143105128
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10906505210 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10906505210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.13929877485287314035796763205679706948686523180499628161446244001534601488291
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10149559619 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10149559619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 21 failures:

Test i2c_host_stress_all has 9 failures.

1.i2c_host_stress_all.84972953942679730160643198105523593156651709661059807115481713808470351759069
Line 136, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20796929176 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1571155

3.i2c_host_stress_all.25569274133003850592635448222997225221361238893626909274546021771501616880695
Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 77748632334 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2795819

... and 7 more failures.

Test i2c_host_mode_toggle has 12 failures.

4.i2c_host_mode_toggle.97203304022211348577575278870642933458801380779997622053267521598391942708123
Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 665752209 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @168722

13.i2c_host_mode_toggle.85580638109896211347506979224582135444323118250809832112141291133407332156634
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  83814450 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @36736

... and 10 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
- Test i2c_target_nack_txstretch has 16 failures.
  - 2.i2c_target_nack_txstretch.13205194229758881880811509909445278813352086467951793891588824060324881957980
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 168606134 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 168606134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_nack_txstretch.77615264341301666066519734461608530596701234268867106599954140215089907005412
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 1217714944 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 1217714944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.79372934211034417002117711825049393110455969440579544286876879304596342086790
Line 123, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1056885976 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1056885976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.92798474012388593204985054032933545130762122277874852184698386800253755408900
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 713249208 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 713249208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

2.i2c_target_stress_all_with_rand_reset.51730969204066569583926283044386332648634863120573462783713888320770162615787
Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 947051949 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 947051949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.49611553141673685117108951237857508120767210888519638537077202552935270366706
Line 96, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1220342766 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1220342766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:

Test i2c_host_mode_toggle has 14 failures.

1.i2c_host_mode_toggle.79644176089585361219975870785884020575360761230759626254221295707186202266815
Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 146110926 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

5.i2c_host_mode_toggle.103134378483556435696427641571501090940342657543229552502183444919999652799770
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 422969218 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 12 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
- Test i2c_target_unexp_stop has 14 failures.
  - 4.i2c_target_unexp_stop.76740822787657114226269211958688297157918406742342644640525045249976629176549
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  96892230 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  96892230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_unexp_stop.57796866125858024023836503630425304642853160574628162702270931105561067802586
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  50588589 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  50588589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:

Test i2c_target_unexp_stop has 8 failures.

11.i2c_target_unexp_stop.67583907221935710259769889123335478601296255633328850769497736348118961520120
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 365486730 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 365486730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.i2c_target_unexp_stop.22602620230910278936367654736988681559322510321250534157173861045954620691441
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/19.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 713027755 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 713027755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 6 failures:
- Test i2c_target_tx_stretch_ctrl has 6 failures.
  - 19.i2c_target_tx_stretch_ctrl.72539066360190421959927532135452383447387608867066153227187598456313052908020
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 20.i2c_target_tx_stretch_ctrl.63087841060232403327641404982278009383819779955759617838671218389966029377595
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
- Test i2c_target_stretch has 3 failures.
  - 7.i2c_target_stretch.5389229046050152291465334577131015990418389650966183402016521082399742680559
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10046373672 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10046373672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.i2c_target_stretch.110862637194245342971113841247925740302663537250885809160352948183689004977645
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/32.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10004347944 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10004347944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.36804970656958424849306913661127563830757970130848734926065144926418005484351
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 3541203869 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 3541203869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.58742290149842171368929578997185542081094089080271787896529141059485585428649
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 640502881 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 640502881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 2 failures.
  - 0.i2c_target_stress_all.2737093892740665588655414270633754004950781307027571843876985118241561117529
    Line 111, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 101973039907 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 101973039907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_stress_all.97361855055607451311074798802503684240106522593479686506022085491727714256640
    Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 44780464389 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 44780464389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

27.i2c_host_stress_all.107985056499134781475369168429814714701010009102563747572620662026580201434984
Line 214, in log /nightly/current_run/scratch/master/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 76734123334 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @20214541

29.i2c_host_stress_all.90473057609131401359236587580839761636559050572724211103474482934986858510356
Line 138, in log /nightly/current_run/scratch/master/i2c-sim-vcs/29.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 18820084382 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4451399

UVM_ERROR (cip_base_vseq.sv:849) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.15244085855619958661444118350888783889560518508238437452423660022024610159432
    Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1116907261 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1116907261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 9.i2c_same_csr_outstanding.85015067906374224704449968352834945628499084425095061645029894851611935798204
    Line 74, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  22077544 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  22077544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 22.i2c_host_mode_toggle.96975100587411708183969266483555965704834833204884476778226027786751118988516
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/22.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_error_intr has 1 failures.
  - 37.i2c_host_error_intr.60395509735678355794903425590661101949437236950490116469130989253959499023772
    Line 97, in log /nightly/current_run/scratch/master/i2c-sim-vcs/37.i2c_host_error_intr/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 44.i2c_host_perf.91998391387347344584974497192305992552666425028467261653901085557137263410336
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/44.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```