KEYMGR Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	40.720s	15.778ms	50	50	100.00
V1	random	keymgr_random	43.460s	17.144ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.540s	144.739us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.330s	33.890us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.500s	1.662ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.530s	372.854us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.010s	205.637us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.330s	33.890us	20	20	100.00
		keymgr_csr_aliasing	9.530s	372.854us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.029m	1.777ms	49	50	98.00
V2	sideload	keymgr_sideload	34.040s	7.240ms	50	50	100.00
		keymgr_sideload_kmac	44.110s	5.747ms	50	50	100.00
		keymgr_sideload_aes	32.220s	1.717ms	50	50	100.00
		keymgr_sideload_otbn	20.430s	937.205us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	22.190s	1.026ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	11.700s	602.895us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.230s	1.450ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.367m	20.493ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	32.930s	5.227ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	24.710s	4.171ms	49	50	98.00
V2	stress_all	keymgr_stress_all	2.750m	7.639ms	50	50	100.00
V2	intr_test	keymgr_intr_test	1.080s	28.770us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.350s	188.880us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.910s	144.390us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.910s	144.390us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.540s	144.739us	5	5	100.00
		keymgr_csr_rw	1.330s	33.890us	20	20	100.00
		keymgr_csr_aliasing	9.530s	372.854us	5	5	100.00
		keymgr_same_csr_outstanding	3.410s	123.035us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.540s	144.739us	5	5	100.00
		keymgr_csr_rw	1.330s	33.890us	20	20	100.00
		keymgr_csr_aliasing	9.530s	372.854us	5	5	100.00
		keymgr_same_csr_outstanding	3.410s	123.035us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
		keymgr_tl_intg_err	8.190s	526.474us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.300s	811.596us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.300s	811.596us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.300s	811.596us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.300s	811.596us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.010s	2.133ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.190s	526.474us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.300s	811.596us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.029m	1.777ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	43.460s	17.144ms	50	50	100.00
		keymgr_csr_rw	1.330s	33.890us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	43.460s	17.144ms	50	50	100.00
		keymgr_csr_rw	1.330s	33.890us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	43.460s	17.144ms	50	50	100.00
		keymgr_csr_rw	1.330s	33.890us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	11.700s	602.895us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	32.930s	5.227ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	32.930s	5.227ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	43.460s	17.144ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	9.640s	2.329ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	17.760s	3.015ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	11.700s	602.895us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	17.760s	3.015ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	17.760s	3.015ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	17.760s	3.015ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.720s	3.205ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	17.760s	3.015ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.290s	2.172ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1084	1110	97.66

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.13	98.26	98.51	100.00	99.01	97.71	91.18

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test keymgr_stress_all_with_rand_reset has 23 failures.

    • 0.keymgr_stress_all_with_rand_reset.57768453350407403070986718554061982040114933493618711941061369223961687968477
      Line 104, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 118194310 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 118194310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.keymgr_stress_all_with_rand_reset.15590019496153944560927791227051921019781625439245337664424318760342689019930
      Line 213, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107804586 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 107804586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_sw_invalid_input has 1 failures.

    • 6.keymgr_sw_invalid_input.40490152517396779281710282085111118618682924932201187747633719749174450715141
      Line 266, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest/run.log

        UVM_ERROR @  42803697 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @  42803697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_cfg_regwen has 1 failures.

    • 35.keymgr_cfg_regwen.20900778321939713342081728803203940920697437237407430402626809213533972385270
      Line 526, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @  46120369 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @  46120369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:

  • Test keymgr_sync_async_fault_cross has 1 failures.

    • 45.keymgr_sync_async_fault_cross.115214294083462019238472323107764649650478421709776616084693126684210966105026
      Line 182, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest/run.log

        UVM_ERROR @ 4170912226 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
        UVM_INFO @ 4170912226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---