KMAC/MASKED Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.279m	3.614ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.490s	61.329us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.590s	34.862us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.500s	2.025ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.110s	1.474ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.220s	1.086ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.590s	34.862us	20	20	100.00
		kmac_csr_aliasing	9.110s	1.474ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.080s	12.375us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.940s	39.612us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.353m	134.516ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.263m	69.415ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.154m	64.034ms	5	5	100.00
		kmac_test_vectors_sha3_256	31.488m	58.023ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.154m	179.404ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.143m	47.478ms	5	5	100.00
		kmac_test_vectors_shake_128	36.855m	73.111ms	5	5	100.00
		kmac_test_vectors_shake_256	34.530m	228.680ms	5	5	100.00
		kmac_test_vectors_kmac	3.730s	150.070us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.360s	88.152us	5	5	100.00
V2	sideload	kmac_sideload	8.715m	81.170ms	50	50	100.00
V2	app	kmac_app	7.430m	66.848ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.986m	26.881ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.113m	39.710ms	50	50	100.00
V2	error	kmac_error	7.881m	56.089ms	50	50	100.00
V2	key_error	kmac_key_error	18.660s	6.915ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.120s	4.962ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.840s	4.017ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	52.780s	2.479ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.070m	42.804ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.990s	597.925us	50	50	100.00
V2	stress_all	kmac_stress_all	32.449m	134.610ms	49	50	98.00
V2	intr_test	kmac_intr_test	1.140s	108.685us	50	50	100.00
V2	alert_test	kmac_alert_test	1.430s	19.891us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.440s	108.692us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.440s	108.692us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.490s	61.329us	5	5	100.00
		kmac_csr_rw	1.590s	34.862us	20	20	100.00
		kmac_csr_aliasing	9.110s	1.474ms	5	5	100.00
		kmac_same_csr_outstanding	3.030s	181.422us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.490s	61.329us	5	5	100.00
		kmac_csr_rw	1.590s	34.862us	20	20	100.00
		kmac_csr_aliasing	9.110s	1.474ms	5	5	100.00
		kmac_same_csr_outstanding	3.030s	181.422us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.360s	91.492us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.360s	91.492us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.360s	91.492us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.360s	91.492us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.520s	503.255us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.404m	8.086ms	5	5	100.00
		kmac_tl_intg_err	4.870s	766.263us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.870s	766.263us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.990s	597.925us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.279m	3.614ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.715m	81.170ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.360s	91.492us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.404m	8.086ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.404m	8.086ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.404m	8.086ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.279m	3.614ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.990s	597.925us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.404m	8.086ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.238m	11.952ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.279m	3.614ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.017m	5.117ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			938	940	99.79

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.33	99.27	94.45	99.89	80.99	97.15	97.83	97.71

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 15.kmac_stress_all.106690909305129280849536387234963948410991131083127487354257996833875407665318
      Line 76, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_stress_all/latest/run.log

        UVM_ERROR @  57104076 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  57104076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 15.kmac_shadow_reg_errors_with_csr_rw.67024214670364633535196620989135198972812616457720357862259382647991462723411
      Line 325, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  42334634 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1949857192 [0x743875a8] vs 1555916367 [0x5cbd664f]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
        UVM_INFO @  42334634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---