e14e4d4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.068m | 7.515ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.490s | 105.680us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.460s | 30.214us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 20.850s | 1.522ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 7.840s | 680.932us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.020s | 91.512us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.460s | 30.214us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 7.840s | 680.932us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.060s | 17.990us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.720s | 82.648us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 47.348m | 504.517ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 14.784m | 66.197ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 34.991m | 347.237ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 29.199m | 207.447ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 22.758m | 66.745ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 19.190s | 925.404us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 36.533m | 298.822ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 29.031m | 239.788ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 2.890s | 111.503us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.030s | 77.326us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 6.220m | 92.709ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 6.139m | 38.119ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 3.787m | 60.351ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 5.534m | 64.185ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 5.364m | 46.967ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 13.230s | 6.815ms | 50 | 50 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 2.543m | 10.016ms | 33 | 50 | 66.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 45.360s | 4.799ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 37.260s | 5.746ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.115m | 68.029ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 42.320s | 2.528ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 26.743m | 332.428ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 1.130s | 28.282us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.210s | 34.826us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.330s | 1.834ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.330s | 1.834ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.490s | 105.680us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.460s | 30.214us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 7.840s | 680.932us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.050s | 384.633us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.490s | 105.680us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.460s | 30.214us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 7.840s | 680.932us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.050s | 384.633us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 723 | 740 | 97.70 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.710s | 102.895us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.710s | 102.895us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.710s | 102.895us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.710s | 102.895us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 5.800s | 2.998ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.353m | 18.448ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.210s | 444.750us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.210s | 444.750us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 42.320s | 2.528ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.068m | 7.515ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 6.220m | 92.709ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.710s | 102.895us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.353m | 18.448ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.353m | 18.448ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.353m | 18.448ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.068m | 7.515ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 42.320s | 2.528ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.353m | 18.448ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 2.283m | 13.588ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.068m | 7.515ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 4.377m | 4.125ms | 6 | 10 | 60.00 |
| V3 | TOTAL | 6 | 10 | 60.00 | |||
| TOTAL | 919 | 940 | 97.77 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.57 | 97.69 | 94.41 | 100.00 | 72.73 | 96.04 | 97.74 | 96.40 |
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 5 failures:
1.kmac_sideload_invalid.53210396284342385031724780550500248678037811565371947629953093085927350703828
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10046118582 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5c42d000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10046118582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_sideload_invalid.93054693053948570266359902669328188419584422770302268837165908755463252459710
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10008057725 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x10e82000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008057725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
2.kmac_stress_all_with_rand_reset.28057040237099104453368667327530710466830344615243853720755380226035997404764
Line 197, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2896757437 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2896757437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_stress_all_with_rand_reset.80214756043002252253305068921840320978751712024637864566437255504190926947844
Line 310, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5919842005 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5919842005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
21.kmac_sideload_invalid.42162008933649435690148537484464442693188476624951267028714498034681698275979
Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10089454069 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xde8f000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10089454069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.kmac_sideload_invalid.102192504823533461595790984032745105643407594884468184584681938400733254632894
Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10084521877 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x42aad000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10084521877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
11.kmac_sideload_invalid.38804636246700442022864080289408195354914516073326638482570270832340517365213
Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10130337345 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3f331000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10130337345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
15.kmac_sideload_invalid.29258632413031366997120050890901629528050453874465914962818909741637302117534
Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/15.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10015770462 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdde6000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10015770462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
16.kmac_sideload_invalid.8814035379057897718965879842915864750854633628493498369545394623587337370288
Line 96, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10805434545 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5f5f7000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10805434545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
18.kmac_sideload_invalid.68584795961829129090280005990948957235747888505767354698962737432235517726387
Line 84, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10194656209 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd1262000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10194656209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
27.kmac_sideload_invalid.111774136129079873230658385569737577775684302700093646553952381453676155791031
Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10060138979 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc5030000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10060138979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
39.kmac_sideload_invalid.39871555406818500962982979486672850789184689283678835823664720338254717755018
Line 88, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/39.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10361407874 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc6e3c000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10361407874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
41.kmac_sideload_invalid.67833119545734376850473399265518363379964519708622481941451148658926031314149
Line 90, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10091709911 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf5c4d000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10091709911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
43.kmac_sideload_invalid.40222675662203015882498768316831632953889005184203945756641509875808822754038
Line 89, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10203034857 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc8ccd000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10203034857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
45.kmac_sideload_invalid.8424449045870183452283932296065085932678723331059660385405697951445015862004
Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/45.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10039814547 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa7ffa000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10039814547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
48.kmac_sideload_invalid.25142791429150573785057261747118362584212854063193067242548861635991326718491
Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10035661275 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x78711000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10035661275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---