e14e4d4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 41.000s | 88.052us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 3.000s | 19.370us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 3.000s | 92.454us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 1.246ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 86.834us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 4.000s | 154.312us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 3.000s | 92.454us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 86.834us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 46.383m | 600.000ms | 27 | 50 | 54.00 |
| V2 | cnt_rollover | cnt_rollover | 1.117m | 2.912ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 41.000s | 45.060us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.780h | 1.408s | 23 | 50 | 46.00 |
| V2 | alert_test | pattgen_alert_test | 37.000s | 89.932us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 3.000s | 28.168us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 5.000s | 79.718us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 5.000s | 79.718us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 3.000s | 19.370us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 92.454us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 86.834us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 37.123us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 3.000s | 19.370us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 92.454us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 86.834us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 37.123us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 290 | 340 | 85.29 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 4.000s | 78.305us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 40.000s | 243.627us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 4.000s | 78.305us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.683m | 22.612ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.700m | 10.041ms | 37 | 50 | 74.00 | |
| TOTAL | 457 | 570 | 80.18 |
UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
0.pattgen_stress_all_with_rand_reset.81696758706704046989435494373451974203079088862943454668272154058613629681438
Line 117, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1353793275 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1353808428 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1353808428 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1354208428 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.28137588629759079244206127210349284938636721762353769482674374348606649263440
Line 129, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 650178377 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 650185733 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 650185733 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 650245973 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 45 more failures.
Job timed out after * minutes has 31 failures:
0.pattgen_perf.111775620972349473435558873509168502761258789642833884126329322071271995665196
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Job timed out after 60 minutes
2.pattgen_perf.28584269874441331099751453255639990457940160792253185962087675448146608838665
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 13 more failures.
0.pattgen_stress_all.39041026219177484165210331817576810027163672104097396424685282466412446032897
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
10.pattgen_stress_all.56577018005769138782738628506969832705614827867185787876587461466215183763515
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 14 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 12 failures:
Test pattgen_stress_all_with_rand_reset has 1 failures.
2.pattgen_stress_all_with_rand_reset.110089952296244541876321592509728628492603259783950977073953150644019225837361
Line 268, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7597462506 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @18190
Test pattgen_stress_all has 11 failures.
4.pattgen_stress_all.3438311556557491555753198458147641522908059244270832575488047929435137926196
Line 149, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 381717170 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10448
19.pattgen_stress_all.47948651926524181718097581968455648600455094069967123709732369374510288645193
Line 132, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_stress_all/latest/run.log
UVM_ERROR @ 404805681 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10218
... and 9 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 8 failures:
1.pattgen_perf.65477353516881195934870170644997466919192004815324895270380959915303448196646
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.pattgen_perf.6216784895713548259876551121682207934472085614459277745367986328065431083284
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
3.pattgen_inactive_level.45371665863475527518730704878696008269906333875248340218363985041163401140623
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10024344484 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xcbecc390, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10024344484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.pattgen_inactive_level.18180294067288042646148641956432950034840474508466015629194067541986771443032
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10031089480 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x33732450, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10031089480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
33.pattgen_inactive_level.115286891552888432432788344790638776124658993266634538270847387009011320959265
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10083448385 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x244e4790, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10083448385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.pattgen_inactive_level.106524210920366144365301916394403248152325681426283220014958890973427601798128
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006472800 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd1a5acd0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10006472800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
36.pattgen_inactive_level.51827468161320758033912456247647164258821268989739133857859175999103741588336
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10030934088 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8066a4d0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10030934088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.pattgen_inactive_level.36324455463967168051911822061406610517019956173297485294142481131355906220443
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10506841731 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcf337fd0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10506841731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 2 failures:
38.pattgen_stress_all_with_rand_reset.95287146813612064457089120241804331803571438366448536338636003644907593289019
Line 129, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 228204961 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
-------------------------------------
Name Type Size Value
43.pattgen_stress_all_with_rand_reset.37890040065949246029085090133677838064394436973208634738069370046560656140913
Line 130, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 772007111 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
16.pattgen_inactive_level.108406207693113164546106947223697431622180862618354728844414405071623883429481
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10040531507 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x217cd8d0, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10040531507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
18.pattgen_inactive_level.15098315189317134128026399600549238381847774575127601928224689708205007082899
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010710857 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x357e3710, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10010710857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
20.pattgen_inactive_level.43711744792618883628680585283972259222269808801398936715731907633374524532388
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002764997 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbe3dd6d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002764997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
24.pattgen_inactive_level.48894544955799119022882519884359497550657728395451781574872663715079196602942
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10547532556 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x18fa74d0, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10547532556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
27.pattgen_inactive_level.12402211353525051744757947715109444056688438560568322782818551828215446352618
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10081223828 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf8930a90, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10081223828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
28.pattgen_inactive_level.108810283683871786639758837803259999981369987070380103231056054317509950351819
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10013117818 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x7a440c10, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10013117818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
34.pattgen_inactive_level.81418006671801749858495903304288095042841332212033975593515577369542807403937
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10003407994 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2449c350, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10003407994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 1 failures:
cov_merge
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: