ROM_CTRL/32KB Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: `e14e4d4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.550s	145.363us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.380s	293.077us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.430s	168.968us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.010s	292.978us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.000s	126.145us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.300s	178.811us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.430s	168.968us	20	20	100.00
		rom_ctrl_csr_aliasing	5.000s	126.145us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.550s	129.153us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.540s	558.530us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.380s	179.199us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	24.420s	2.145ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.850s	305.406us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	6.370s	168.319us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.540s	218.053us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.540s	218.053us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.380s	293.077us	5	5	100.00
		rom_ctrl_csr_rw	6.430s	168.968us	20	20	100.00
		rom_ctrl_csr_aliasing	5.000s	126.145us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.060s	171.842us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.380s	293.077us	5	5	100.00
		rom_ctrl_csr_rw	6.430s	168.968us	20	20	100.00
		rom_ctrl_csr_aliasing	5.000s	126.145us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.060s	171.842us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	24.350s	3.448ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.336m	2.233ms	0	5	0.00
		rom_ctrl_tl_intg_err	1.045m	2.822ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.336m	2.233ms	0	5	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.336m	2.233ms	0	5	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.336m	2.233ms	0	5	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.336m	2.233ms	0	5	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.550s	145.363us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.550s	145.363us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.550s	145.363us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.045m	2.822ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
		rom_ctrl_kmac_err_chk	7.850s	305.406us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.055m	15.635ms	17	20	85.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	24.350s	3.448ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.336m	2.233ms	0	5	0.00
V2S		TOTAL			57	65	87.69
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.971m	3.011ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			258	266	96.99

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 4 failures:

Test rom_ctrl_sec_cm has 4 failures.

0.rom_ctrl_sec_cm.71632434588130452680451433475335133597994699042972904459873560529619672334762
Line 440, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 72641307ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 72641307ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 72641307ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))

1.rom_ctrl_sec_cm.65517167129666181713021668044501546528995117815321967554536489211879772537543
Line 305, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 20120729ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 20120729ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 20120729ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))

... and 2 more failures.

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.
  - 2.rom_ctrl_corrupt_sig_fatal_chk.95076953286277559679644228339896492294808259063044118974996533770805626011074
    Line 93, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1563239417 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1563239417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.rom_ctrl_corrupt_sig_fatal_chk.96953894174524936454325380684402069510820790892804760476212108651526869351727
    Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1906595525 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1906595525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

4.rom_ctrl_sec_cm.43681069132414482747576462453024775089442580621428731500790524466758574444978
Line 245, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 46351809ps failed at 46351809ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 46372217ps failed at 46372217ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'