ROM_CTRL/64KB Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.860s	894.512us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.160s	291.924us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.640s	1.386ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.990s	297.823us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	9.620s	231.829us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.610s	293.309us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.640s	1.386ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.620s	231.829us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.610s	1.630ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.280s	1.056ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.240s	308.208us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	51.090s	1.123ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.180s	383.887us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	11.880s	286.521us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.520s	292.210us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.520s	292.210us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.160s	291.924us	5	5	100.00
		rom_ctrl_csr_rw	15.640s	1.386ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.620s	231.829us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.890s	4.346ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.160s	291.924us	5	5	100.00
		rom_ctrl_csr_rw	15.640s	1.386ms	20	20	100.00
		rom_ctrl_csr_aliasing	9.620s	231.829us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.890s	4.346ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.077m	45.745ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	8.696m	4.432ms	3	5	60.00
		rom_ctrl_tl_intg_err	1.966m	793.034us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	8.696m	4.432ms	3	5	60.00
V2S	prim_count_check	rom_ctrl_sec_cm	8.696m	4.432ms	3	5	60.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	8.696m	4.432ms	3	5	60.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	8.696m	4.432ms	3	5	60.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.860s	894.512us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.860s	894.512us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.860s	894.512us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.966m	793.034us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
		rom_ctrl_kmac_err_chk	16.180s	383.887us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.269m	25.619ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.077m	45.745ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	8.696m	4.432ms	3	5	60.00
V2S		TOTAL			63	65	96.92
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	9.201m	14.278ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			264	266	99.25

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:
  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.99796867907394224689132235779620509985344504245379488234370982102267695608111
      Line 361, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 238400060ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 238400060ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 238400060ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

    • 4.rom_ctrl_sec_cm.3008537581533217211797053698486431788449237770376180229632622211724718555116
      Line 232, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 35047161ps failed at 35047161ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 35088828ps failed at 35088828ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'