RV_TIMER Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.930s	16.997us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.840s	16.639us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.830s	14.982us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.730s	285.774us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.040s	24.451us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.260s	94.419us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.830s	14.982us	20	20	100.00
		rv_timer_csr_aliasing	1.040s	24.451us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	12.110s	38.589ms	20	20	100.00
V2	disabled	rv_timer_disabled	5.250s	3.243ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	26.791m	7.388s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	26.791m	7.388s	10	10	100.00
V2	stress	rv_timer_stress_all	5.100s	4.297ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.850s	51.867us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.720s	11.498us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.370s	639.647us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.370s	639.647us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.840s	16.639us	5	5	100.00
		rv_timer_csr_rw	0.830s	14.982us	20	20	100.00
		rv_timer_csr_aliasing	1.040s	24.451us	5	5	100.00
		rv_timer_same_csr_outstanding	0.970s	36.149us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.840s	16.639us	5	5	100.00
		rv_timer_csr_rw	0.830s	14.982us	20	20	100.00
		rv_timer_csr_aliasing	1.040s	24.451us	5	5	100.00
		rv_timer_same_csr_outstanding	0.970s	36.149us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.280s	828.768us	5	5	100.00
		rv_timer_tl_intg_err	1.330s	333.494us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.330s	333.494us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	0.930s	86.523us	10	10	100.00
V3	max_value	rv_timer_max	0.890s	21.465us	10	10	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	47.730s	26.742ms	20	20	100.00
V3		TOTAL			40	40	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.91	100.00	100.00	78.66	--	100.00	96.82	100.00