SPI_DEVICE/1R1W Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: `e14e4d4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.062m	85.157ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.680s	38.598us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.070s	464.833us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.260s	2.729ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.160s	3.243ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.960s	55.787us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.070s	464.833us	20	20	100.00
		spi_device_csr_aliasing	20.160s	3.243ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.010s	11.443us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.410s	110.269us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.130s	21.234us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.040s	2.898us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.030s	4.510us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	7.450s	636.424us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.450s	636.424us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.000s	42.284ms	50	50	100.00
		spi_device_tpm_sts_read	1.470s	126.453us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.150s	54.883ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.660s	7.525ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.260s	53.312ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.260s	53.312ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	24.880s	11.037ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	24.880s	11.037ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.880s	11.037ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	24.880s	11.037ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.880s	11.037ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.360s	39.968ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.244m	26.332ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.244m	26.332ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.244m	26.332ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	51.500s	21.216ms	50	50	100.00
		spi_device_read_buffer_direct	13.760s	9.117ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.244m	26.332ms	50	50	100.00
		spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.718m	71.986ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.330s	2.272ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.330s	2.272ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.062m	85.157ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.478m	490.569ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.601m	126.121ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.060s	16.827us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.080s	13.065us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.830s	1.408ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.830s	1.408ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.680s	38.598us	5	5	100.00
		spi_device_csr_rw	3.070s	464.833us	20	20	100.00
		spi_device_csr_aliasing	20.160s	3.243ms	5	5	100.00
		spi_device_same_csr_outstanding	4.660s	642.700us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.680s	38.598us	5	5	100.00
		spi_device_csr_rw	3.070s	464.833us	20	20	100.00
		spi_device_csr_aliasing	20.160s	3.243ms	5	5	100.00
		spi_device_same_csr_outstanding	4.660s	642.700us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.700s	134.795us	5	5	100.00
		spi_device_tl_intg_err	24.300s	12.681ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.300s	12.681ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.214m	75.323ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.62	99.11	96.56	71.19	89.36	98.40	94.43	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.90590205155731733268824470097886255261083243843548035462924818791380897332150
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2186432 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[62])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2186432 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2186432 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[958])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.84789404066806089278674456603193346999903696525945454785984696736827984423929
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1986402 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[35])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1986402 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1986402 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[931])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])

has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.82987359443873268664104359165241771235573463377571023899378607448484736629845
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   1880991 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x60bac2 [11000001011101011000010] vs 0x0 [0])
  UVM_ERROR @   1955991 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6d1802 [11011010001100000000010] vs 0x0 [0])
  UVM_ERROR @   1966991 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x522f9b [10100100010111110011011] vs 0x0 [0])
  UVM_ERROR @   1983991 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfa2910 [111110100010100100010000] vs 0x0 [0])
  UVM_ERROR @   2067991 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x21faf [100001111110101111] vs 0x0 [0])