SPI_DEVICE/2P Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.744m	33.679ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.680s	176.630us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.720s	148.581us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.310s	1.005ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.080s	1.897ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.610s	194.607us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.720s	148.581us	20	20	100.00
		spi_device_csr_aliasing	17.080s	1.897ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.020s	57.431us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.520s	56.683us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.170s	88.353us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.440s	33.531us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.020s	17.622us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.920s	734.985us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.920s	734.985us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.140s	6.685ms	50	50	100.00
		spi_device_tpm_sts_read	1.630s	176.868us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	36.730s	7.244ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.740s	62.581ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.000s	42.385ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.000s	42.385ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	21.300s	9.398ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	21.300s	9.398ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	21.300s	9.398ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	21.300s	9.398ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	21.300s	9.398ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.560s	9.466ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.216m	86.062ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.216m	86.062ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.216m	86.062ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.362m	30.471ms	50	50	100.00
		spi_device_read_buffer_direct	17.760s	1.749ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.216m	86.062ms	50	50	100.00
		spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.623m	465.079ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.200s	11.401ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	24.200s	11.401ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.744m	33.679ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.133m	68.317ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.869m	112.971ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.110s	188.709us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.090s	43.114us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.400s	666.311us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.400s	666.311us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.680s	176.630us	5	5	100.00
		spi_device_csr_rw	2.720s	148.581us	20	20	100.00
		spi_device_csr_aliasing	17.080s	1.897ms	5	5	100.00
		spi_device_same_csr_outstanding	3.960s	169.748us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.680s	176.630us	5	5	100.00
		spi_device_csr_rw	2.720s	148.581us	20	20	100.00
		spi_device_csr_aliasing	17.080s	1.897ms	5	5	100.00
		spi_device_same_csr_outstanding	3.960s	169.748us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	1.750s	195.861us	5	5	100.00
		spi_device_tl_intg_err	19.410s	4.631ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.410s	4.631ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.059m	1.414s	50	50	100.00
		TOTAL			1150	1151	99.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.16	99.17	96.68	74.78	89.36	98.49	94.41	99.26

Failure Buckets

• UVM_ERROR (spi_device_scoreboard.sv:2236) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
  • Test spi_device_cfg_cmd has 1 failures.

    • 43.spi_device_cfg_cmd.15303566938988296117733519082998538898477459051677158322742224093177762789289
      Line 76, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest/run.log

        UVM_ERROR @ 361811600 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x85e3e) != exp '{'{other_status:'h2213c1, wel:'h0, busy:'h0}, '{other_status:'h2213c1, wel:'h0, busy:'h0}, '{other_status:'h2178f, wel:'h0, busy:'h0}, '{other_status:'h2213c1, wel:'h0, busy:'h0}, '{other_status:'h2178f, wel:'h0, busy:'h0}}
        UVM_INFO @ 361983317 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xb7
        UVM_ERROR @ 362750993 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x85e3e) != exp '{'{other_status:'h2213c1, wel:'h0, busy:'h0}, '{other_status:'h2178f, wel:'h0, busy:'h0}, '{other_status:'h2178f, wel:'h0, busy:'h0}, '{other_status:'h2213c1, wel:'h0, busy:'h0}, '{other_status:'h2178f, wel:'h0, busy:'h0}}
        UVM_INFO @ 364235840 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0xe9
        UVM_INFO @ 697518335 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0x4