SPI_HOST Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: `e14e4d4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.183m	3.436ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	17.900us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	34.199us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	39.045us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	27.377us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	24.112us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	34.199us	20	20	100.00
		spi_host_csr_aliasing	3.000s	27.377us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	42.927us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	57.159us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	4.000s	126.917us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	36.000s	667.578us	50	50	100.00
		spi_host_error_cmd	3.000s	32.376us	50	50	100.00
		spi_host_event	5.017m	56.155ms	50	50	100.00
V2	clock_rate	spi_host_speed	11.000s	346.001us	50	50	100.00
V2	speed	spi_host_speed	11.000s	346.001us	50	50	100.00
V2	chip_select_timing	spi_host_speed	11.000s	346.001us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.133m	8.523ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	407.410us	50	50	100.00
V2	cpol_cpha	spi_host_speed	11.000s	346.001us	50	50	100.00
V2	full_cycle	spi_host_speed	11.000s	346.001us	50	50	100.00
V2	duplex	spi_host_smoke	2.183m	3.436ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.183m	3.436ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.633m	5.588ms	50	50	100.00
V2	spien	spi_host_spien	6.483m	10.813ms	50	50	100.00
V2	stall	spi_host_status_stall	22.950m	116.606ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	34.000s	1.289ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	36.000s	667.578us	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	24.615us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	54.614us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	250.842us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	250.842us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	17.900us	5	5	100.00
		spi_host_csr_rw	3.000s	34.199us	20	20	100.00
		spi_host_csr_aliasing	3.000s	27.377us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	32.870us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	17.900us	5	5	100.00
		spi_host_csr_rw	3.000s	34.199us	20	20	100.00
		spi_host_csr_aliasing	3.000s	27.377us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	32.870us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	221.880us	20	20	100.00
		spi_host_sec_cm	3.000s	82.372us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	221.880us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	8.133m	61.619ms	9	10	90.00
		TOTAL			838	840	99.76

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 2.spi_host_upper_range_clkdiv.11486433357599400486450567882542071632496037874440276076577935965283666165395
    Line 112, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

15.spi_host_status_stall.47090318870405663133995727653740652612474318245534435843251313780512701157469
Line 7837, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 8964899905 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 8964899905 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=8964900000 ps
  UVM_INFO @ 8964899905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 1 failures:

Test spi_host has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/spi_host-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test spi_host has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/spi_host-sim-xcelium/cov_report/cov_report.log