SRAM_CTRL/MAIN Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.759m	2.709ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.000s	14.779us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.000s	15.338us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.660s	149.800us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.050s	31.796us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.560s	359.113us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.000s	15.338us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	31.796us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.132m	106.339ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.003m	15.255ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.410m	51.043ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.952m	5.839ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	39.630m	1.151s	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.927m	18.024ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.927m	67.238ms	50	50	100.00
V2	executable	sram_ctrl_executable	16.706m	47.667ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.721m	995.821us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.952m	26.820ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.608m	3.175ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.670m	811.277us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.767m	4.148ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.834m	99.316ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.050s	5.604ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.175h	517.996ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.020s	12.348us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.970s	191.707us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.970s	191.707us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.000s	14.779us	5	5	100.00
		sram_ctrl_csr_rw	1.000s	15.338us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	31.796us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.090s	24.970us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.000s	14.779us	5	5	100.00
		sram_ctrl_csr_rw	1.000s	15.338us	20	20	100.00
		sram_ctrl_csr_aliasing	1.050s	31.796us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.090s	24.970us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.214m	46.865ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.980s	4.280us	0	5	0.00
		sram_ctrl_tl_intg_err	2.820s	673.130us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.980s	4.280us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.820s	673.130us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.834m	99.316ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.834m	99.316ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.000s	15.338us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	16.706m	47.667ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	16.706m	47.667ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	16.706m	47.667ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.927m	67.238ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.180s	9.491ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.214m	46.865ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.540s	5.544ms	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.759m	2.709ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.759m	2.709ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	16.706m	47.667ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.980s	4.280us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.927m	67.238ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.980s	4.280us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.980s	4.280us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.759m	2.709ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.980s	4.280us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.678m	3.693ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1168	1190	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.11	92.90	85.46	100.00	98.02	95.83	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
  • Test sram_ctrl_readback_err has 11 failures.

    • 2.sram_ctrl_readback_err.13157336515287282561326088852901124707853690134430688449053421574569466474333
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2988352499 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x22) != exp (0x1)
        UVM_INFO @ 2988352499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.78805184433435977276294241481518744809738921786137533785074146345558255825472
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2740845738 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xd) != exp (0x63)
        UVM_INFO @ 2740845738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:
  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 0.sram_ctrl_mubi_enc_err.107361668024077945482343554340288467554595314013917798212016561990825567687350
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2436279702 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2436279702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.sram_ctrl_mubi_enc_err.5553290334197045107955686573933684692820457032469859610846270367613845089965
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1469213532 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1469213532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.91632314797772487467387092051062273291346546374028426507101351448531895893040
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8393625 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8393625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.47479705673652733747281329746520333470681324186588309710918809239746190082488
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4280311 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4280311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.16528578850346833571797136250510581648963037401732766186875249329057790274598
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   7983092 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   7983092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---