UART Simulation Results

Sunday September 14 2025 00:09:11 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	24.110s	5.385ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	3.180s	1.033ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.960s	20.062us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.540s	667.752us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.080s	54.930us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.580s	94.403us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.960s	20.062us	20	20	100.00
		uart_csr_aliasing	1.080s	54.930us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.601m	180.797ms	50	50	100.00
V2	parity	uart_smoke	24.110s	5.385ms	50	50	100.00
		uart_tx_rx	5.601m	180.797ms	50	50	100.00
V2	parity_error	uart_intr	7.219m	206.827ms	50	50	100.00
		uart_rx_parity_err	6.300m	143.722ms	50	50	100.00
V2	watermark	uart_tx_rx	5.601m	180.797ms	50	50	100.00
		uart_intr	7.219m	206.827ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.595m	192.687ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.346m	140.200ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.404m	90.806ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.219m	206.827ms	50	50	100.00
V2	rx_break_err	uart_intr	7.219m	206.827ms	50	50	100.00
V2	rx_timeout	uart_intr	7.219m	206.827ms	50	50	100.00
V2	perf	uart_perf	21.306m	30.032ms	48	50	96.00
V2	sys_loopback	uart_loopback	22.190s	8.576ms	50	50	100.00
V2	line_loopback	uart_loopback	22.190s	8.576ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	2.281m	67.291ms	13	50	26.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	51.640s	41.026ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	34.110s	12.831ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.070m	6.801ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.598m	143.078ms	50	50	100.00
V2	stress_all	uart_stress_all	42.246m	321.444ms	39	50	78.00
V2	alert_test	uart_alert_test	0.880s	39.394us	50	50	100.00
V2	intr_test	uart_intr_test	0.950s	13.266us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.380s	44.188us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.380s	44.188us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	3.180s	1.033ms	5	5	100.00
		uart_csr_rw	0.960s	20.062us	20	20	100.00
		uart_csr_aliasing	1.080s	54.930us	5	5	100.00
		uart_same_csr_outstanding	1.070s	27.839us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	3.180s	1.033ms	5	5	100.00
		uart_csr_rw	0.960s	20.062us	20	20	100.00
		uart_csr_aliasing	1.080s	54.930us	5	5	100.00
		uart_same_csr_outstanding	1.070s	27.839us	20	20	100.00
V2		TOTAL			1039	1090	95.32
V2S	tl_intg_err	uart_sec_cm	1.280s	70.240us	5	5	100.00
		uart_tl_intg_err	1.720s	91.815us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.720s	91.815us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.684m	8.247ms	90	100	90.00
V3		TOTAL			90	100	90.00
		TOTAL			1259	1320	95.38

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.53	99.48	98.25	74.67	--	98.14	97.12	99.53

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 23 failures:

  • Test uart_noise_filter has 18 failures.

    • 0.uart_noise_filter.3008504669457779890759089660924231394833708745099844205694839488428434499756
      Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 36899500940 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 37221045179 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 37221045179 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 37223336864 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 37223336864 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • 3.uart_noise_filter.9905820364470179191711198021990450339798722441649368739628598823804596798321
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log

        UVM_ERROR @ 2744308454 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2744748454 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2901788454 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 2901788454 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2902948454 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
      

    • ... and 16 more failures.

  • Test uart_stress_all has 3 failures.

    • 25.uart_stress_all.86629445399021381873855266626755250138567903162798129499191838322961281441081
      Line 87, in log /nightly/current_run/scratch/master/uart-sim-vcs/25.uart_stress_all/latest/run.log

        UVM_ERROR @ 115809602122 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 115860041236 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 115860041236 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
        UVM_ERROR @ 115903011361 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @ 115903021778 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
      

    • 44.uart_stress_all.83539047961500523342976040129366618443620307991733301728419176898719894716834
      Line 90, in log /nightly/current_run/scratch/master/uart-sim-vcs/44.uart_stress_all/latest/run.log

        UVM_ERROR @ 86592533311 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 86592533311 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 88024008070 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 88024008070 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 88865197705 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (211 [0xd3] vs 166 [0xa6]) reg name: uart_reg_block.rdata
      

    • ... and 1 more failures.

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 42.uart_stress_all_with_rand_reset.27501343197086913103592353424877241876866247811768816715050996230821653653964
      Line 97, in log /nightly/current_run/scratch/master/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 291135513 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 291135513 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 307042272 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/365
        UVM_ERROR @ 380680045 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 380680045 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • 83.uart_stress_all_with_rand_reset.111799848645332754093335912054770265168392863233313124251990912132055018670481
      Line 98, in log /nightly/current_run/scratch/master/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1004176034 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1004676034 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1004816034 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_INFO @ 1038506034 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/295
        UVM_ERROR @ 1099486034 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 17 failures:

  • Test uart_stress_all_with_rand_reset has 4 failures.

    • 13.uart_stress_all_with_rand_reset.58829831455312619925837946217873256817001005868371027418422873662252315021671
      Line 171, in log /nightly/current_run/scratch/master/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4151707596 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 4151749263 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 4151763152 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 4151804819 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 4151818708 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 75 [0x4b]) reg name: uart_reg_block.rdata
      

    • 33.uart_stress_all_with_rand_reset.71320062441435007093955098978550790846161800958348978258152364247376258752242
      Line 94, in log /nightly/current_run/scratch/master/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4204363432 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 4204679224 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 4204731856 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (78 [0x4e] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_INFO @ 4447575904 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/560
        UVM_INFO @ 4642840624 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/560
      

    • ... and 2 more failures.

  • Test uart_noise_filter has 9 failures.

    • 16.uart_noise_filter.113859751627727397393715874474902088405919050729464598735448926448562945713069
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/16.uart_noise_filter/latest/run.log

        UVM_ERROR @ 20265399161 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 20265409799 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 20265420437 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 20265431075 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 20265441713 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

    • 20.uart_noise_filter.56526852913329795920710528063291446183099772050492609643810621459962543123051
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/20.uart_noise_filter/latest/run.log

        UVM_ERROR @ 77828732684 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0
        UVM_ERROR @ 77828809607 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 77828886530 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (151 [0x97] vs 223 [0xdf]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 77828963453 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 77829040376 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (151 [0x97] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

    • ... and 7 more failures.

  • Test uart_stress_all has 4 failures.

    • 16.uart_stress_all.67707234668234552079798391687951280831500908154303145153172778066811754096891
      Line 90, in log /nightly/current_run/scratch/master/uart-sim-vcs/16.uart_stress_all/latest/run.log

        UVM_ERROR @ 214643820198 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 214643963055 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 214644248769 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (59 [0x3b] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 214644391626 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 214645391625 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (59 [0x3b] vs 254 [0xfe]) reg name: uart_reg_block.rdata
      

    • 24.uart_stress_all.93691205332401461950094460593789587280214783257679561128249873234107842781227
      Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/24.uart_stress_all/latest/run.log

        UVM_ERROR @ 5427437416 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 5427447416 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 5427457416 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (158 [0x9e] vs 243 [0xf3]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 5427467416 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 5427477416 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (158 [0x9e] vs 253 [0xfd]) reg name: uart_reg_block.rdata
      

    • ... and 2 more failures.

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 10 failures:

  • Test uart_noise_filter has 7 failures.

    • 1.uart_noise_filter.7995520694316776661467223856093465480545132165589516032629339225525994808883
      Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log

        UVM_ERROR @ 8216051400 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 8216051400 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 8216051400 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 8704305306 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 13,                                 clk_pulses: 0
        UVM_ERROR @ 8704471974 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 191 [0xbf]) reg name: uart_reg_block.rdata
      

    • 17.uart_noise_filter.70237943820263662902332477771604607641900462448050382574410356980080434490379
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/17.uart_noise_filter/latest/run.log

        UVM_ERROR @  89128373 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @  89128373 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  94512206 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @  98946545 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @  98946545 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 5 more failures.

  • Test uart_stress_all has 2 failures.

    • 13.uart_stress_all.10106369615765028378673454043022479766147859606731275763154407873006390028774
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/13.uart_stress_all/latest/run.log

        UVM_ERROR @ 335246289 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 335246289 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 337162948 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 337162948 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 338329610 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
      

    • 33.uart_stress_all.111931695881451253006760165168417461324461822665716357048953304275256010267551
      Line 79, in log /nightly/current_run/scratch/master/uart-sim-vcs/33.uart_stress_all/latest/run.log

        UVM_ERROR @ 58889343161 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 58889343161 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 58889343161 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 58905443161 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 58905473161 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (50 [0x32] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 69.uart_stress_all_with_rand_reset.47650009035286484712008986752509300275623653098629422464095738887936755930336
      Line 134, in log /nightly/current_run/scratch/master/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22820279222 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 22820279222 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 22820279222 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 23650135535 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/106
        UVM_ERROR @ 24131135054 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 20,                                 clk_pulses: 0
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 5 failures:

  • Test uart_stress_all has 2 failures.

    • 17.uart_stress_all.70392031419311352161167694726101770942934946392502621906962506709459737942522
      Line 91, in log /nightly/current_run/scratch/master/uart-sim-vcs/17.uart_stress_all/latest/run.log

        UVM_ERROR @ 23516873204 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 23516873204 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 23516873204 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
        UVM_ERROR @ 23535581687 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 23535581687 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • 35.uart_stress_all.110511226700370368203706208539963131143104862691140221759415590969659696036077
      Line 156, in log /nightly/current_run/scratch/master/uart-sim-vcs/35.uart_stress_all/latest/run.log

        UVM_ERROR @ 27987384829 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 27989322298 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 28289150834 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 28289171667 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 28289192500 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (175 [0xaf] vs 223 [0xdf]) reg name: uart_reg_block.rdata
      

  • Test uart_noise_filter has 3 failures.

    • 21.uart_noise_filter.109328434044052397242537113431604029594807305369015720375866926895667780565743
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/21.uart_noise_filter/latest/run.log

        UVM_ERROR @  96065830 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @  96065830 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
        UVM_ERROR @ 203645830 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 203645830 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
        UVM_ERROR @ 203645830 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
      

    • 24.uart_noise_filter.47830655300583245591145644244260018687313984194930425948723712099187509423002
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/24.uart_noise_filter/latest/run.log

        UVM_ERROR @ 205646635 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 411523282 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 415064977 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 446690230 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 446690230 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

    • ... and 1 more failures.

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 3 failures:

  • Test uart_perf has 2 failures.

    • 34.uart_perf.67589940683537393137547738112264205640260175084175551770760156237458052637154
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/34.uart_perf/latest/run.log

        UVM_ERROR @ 7666432779 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 7726233400 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/5
        UVM_INFO @ 8155479887 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/5
        UVM_INFO @ 13554078571 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/5
        UVM_INFO @ 14273012579 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/5
      

    • 47.uart_perf.36403430685280075492989198166332177382448277279334986418631587471326318585945
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/47.uart_perf/latest/run.log

        UVM_ERROR @ 9314250677 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 17996019376 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/7
        UVM_INFO @ 24480785270 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/7
        UVM_INFO @ 24481716327 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/7
        UVM_INFO @ 29794652152 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/7
      

  • Test uart_fifo_reset has 1 failures.

    • 234.uart_fifo_reset.58308322715447655083565194299470921544572228877477518473219721544875426021158
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/234.uart_fifo_reset/latest/run.log

        UVM_ERROR @    886145 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 665496145 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5
        UVM_INFO @ 1621356145 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5
        UVM_INFO @ 12274706145 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5
        UVM_INFO @ 13142786145 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5
      

• UVM_ERROR (cip_base_vseq.sv:849) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 44.uart_stress_all_with_rand_reset.31899979150906115984084168449937761552170743042503088624210250106665480092890
      Line 131, in log /nightly/current_run/scratch/master/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7374317764 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 7374317764 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 5/10
        UVM_INFO @ 7374442765 ps: (cip_base_vseq.sv:873) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 5/10
      

    • 59.uart_stress_all_with_rand_reset.84719744979803589545027582256473229449458550699966621000539773890999681160528
      Line 138, in log /nightly/current_run/scratch/master/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3618168513 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3618168513 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 7/10
        UVM_INFO @ 3618290961 ps: (cip_base_vseq.sv:873) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 7/10
      

• UVM_ERROR (cip_base_vseq.sv:945) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 5.uart_stress_all_with_rand_reset.52896769650699098264437643225811563645821923255784048874229971004730844985440
      Line 135, in log /nightly/current_run/scratch/master/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1196245265 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1196247646 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1196247646 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 8/10
        UVM_INFO @ 1196259758 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2