1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 29.034s | 42 | 50 | 84.00 | |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 19.993s | 4 | 5 | 80.00 | |
| V1 | csr_rw | adc_ctrl_csr_rw | 14.297s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 1.122m | 52.466ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 3.200s | 1.131ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 22.492s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 14.297s | 19 | 20 | 95.00 | |
| adc_ctrl_csr_aliasing | 3.200s | 1.131ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 92 | 105 | 87.62 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 14.604m | 493.512ms | 43 | 50 | 86.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 15.018m | 478.375ms | 41 | 50 | 82.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 17.975m | 490.976ms | 45 | 50 | 90.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 13.867m | 496.928ms | 43 | 50 | 86.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 17.688m | 659.272ms | 43 | 50 | 86.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 18.419m | 619.803ms | 42 | 50 | 84.00 |
| V2 | filters_both | adc_ctrl_filters_both | 17.000m | 529.527ms | 41 | 50 | 82.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 16.170m | 499.569ms | 26 | 50 | 52.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 22.084s | 41 | 50 | 82.00 | |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 2.028m | 37.007ms | 42 | 50 | 84.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 3.898m | 124.010ms | 44 | 50 | 88.00 |
| V2 | stress_all | adc_ctrl_stress_all | 19.905m | 622.078ms | 42 | 50 | 84.00 |
| V2 | alert_test | adc_ctrl_alert_test | 29.226s | 37 | 50 | 74.00 | |
| V2 | intr_test | adc_ctrl_intr_test | 28.518s | 46 | 50 | 92.00 | |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 32.870s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 32.870s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 19.993s | 4 | 5 | 80.00 | |
| adc_ctrl_csr_rw | 14.297s | 19 | 20 | 95.00 | |||
| adc_ctrl_csr_aliasing | 3.200s | 1.131ms | 5 | 5 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 20.367s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 19.993s | 4 | 5 | 80.00 | |
| adc_ctrl_csr_rw | 14.297s | 19 | 20 | 95.00 | |||
| adc_ctrl_csr_aliasing | 3.200s | 1.131ms | 5 | 5 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 20.367s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 612 | 740 | 82.70 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 17.780s | 8.202ms | 5 | 5 | 100.00 |
| adc_ctrl_tl_intg_err | 15.650s | 8.353ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 15.650s | 8.353ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 10.475m | 10.000s | 38 | 50 | 76.00 |
| V3 | TOTAL | 38 | 50 | 76.00 | |||
| TOTAL | 767 | 920 | 83.37 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.20 | 99.05 | 96.03 | 100.00 | 100.00 | 98.64 | 95.95 | 90.73 |
Job returned non-zero exit code has 115 failures:
Test adc_ctrl_same_csr_outstanding has 2 failures.
1.adc_ctrl_same_csr_outstanding.27929891302398840312916489679755636521253038308252231206658799479275242731328
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
9.adc_ctrl_same_csr_outstanding.44382849325272740601721451436061403440747745199256597224661756427097479268228
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:30 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test adc_ctrl_csr_hw_reset has 1 failures.
2.adc_ctrl_csr_hw_reset.24805721130118642091465041743087379213435884023337780594462957386076899298915
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test adc_ctrl_csr_bit_bash has 1 failures.
3.adc_ctrl_csr_bit_bash.33649794332120790767516760816482552415000407064523932498516017146099833006061
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test adc_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
3.adc_ctrl_csr_mem_rw_with_rand_reset.55907428034458033135073693717257485549295947555442103214705579685286853297931
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
4.adc_ctrl_csr_mem_rw_with_rand_reset.30755760998378457515464106837585801221324806267349640365285445298079229270002
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test adc_ctrl_intr_test has 3 failures.
4.adc_ctrl_intr_test.111830914971752440070161179472707200404424962940965966394905888609163692382984
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
15.adc_ctrl_intr_test.42739732983295728128722095310847772229130370473598061047522928709603129753521
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:30 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
... and 17 more tests.
Job timed out after * minutes has 15 failures:
Test adc_ctrl_stress_all has 1 failures.
10.adc_ctrl_stress_all.35185080190923497964371113395319744877591915102354112168647571447541831532746
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest/run.log
Job timed out after 180 minutes
Test adc_ctrl_intr_test has 1 failures.
11.adc_ctrl_intr_test.106221851118213205698169293935589191649913464299060745783971450846883548048656
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest/run.log
Job timed out after 60 minutes
Test adc_ctrl_fsm_reset has 1 failures.
12.adc_ctrl_fsm_reset.114037736414571917007118366797340982011959419499678294820974378514454229676587
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest/run.log
Job timed out after 60 minutes
Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
12.adc_ctrl_stress_all_with_rand_reset.32520796002149887537760929039719902942814404939401895884556210074270979411928
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
Test adc_ctrl_filters_wakeup_fixed has 3 failures.
13.adc_ctrl_filters_wakeup_fixed.99322322112635978122145899134670332622629033871667160799893675606228553671877
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest/run.log
Job timed out after 60 minutes
21.adc_ctrl_filters_wakeup_fixed.36534390935942358876342537317271040418127848739673610408272339147296709452074
Log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
... and 5 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
Test adc_ctrl_clock_gating has 9 failures.
1.adc_ctrl_clock_gating.99458362039720317530722363111114822363420180892383933012244883787422967496656
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.adc_ctrl_clock_gating.53793815280390829578614139585735716324087060586821188647841756751813596397718
Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest/run.log
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test adc_ctrl_stress_all_with_rand_reset has 2 failures.
8.adc_ctrl_stress_all_with_rand_reset.57898429298678770372503843721380480343466839997599465781076671703162186788936
Line 201, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.adc_ctrl_stress_all_with_rand_reset.110351250501794450170063033587514292929460776440118993915894229407488371803078
Line 209, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test adc_ctrl_filters_both has 1 failures.
31.adc_ctrl_filters_both.109238777033261070721742090850624723859164322157335599791227402348938642813080
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:
Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
0.adc_ctrl_stress_all_with_rand_reset.33616979621736150006685710776412296357081996576509065212155392547107367139496
Line 190, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 47297178693 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 47297178693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test adc_ctrl_stress_all has 1 failures.
9.adc_ctrl_stress_all.49158138767592051439481934086579244523673909181147933419168288376377880325641
Line 261, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 51312087375 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 51312087375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test adc_ctrl_clock_gating has 5 failures.
10.adc_ctrl_clock_gating.96589167285702782912395188008888972103096587959786739481187463232205502248031
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest/run.log
UVM_ERROR @ 4572207194 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 4572207194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.adc_ctrl_clock_gating.16216468344248440413804873828701566182559396737907657609299589349047029283505
Line 158, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest/run.log
UVM_ERROR @ 44304405997 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 44304405997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 3 failures:
Test adc_ctrl_filters_both has 1 failures.
3.adc_ctrl_filters_both.70957904025997510257764561725771019380829009341666788257635410857532729085138
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest/run.log
UVM_ERROR @ 189105560534 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 189105560534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test adc_ctrl_clock_gating has 1 failures.
7.adc_ctrl_clock_gating.6659143183672839102244589991875666695431075483423949703817521499111694575262
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log
UVM_ERROR @ 188101709763 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 188101709763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test adc_ctrl_stress_all has 1 failures.
8.adc_ctrl_stress_all.91677671875697290121696534183161818113960073573028179122569481292356837765697
Line 164, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 163714088464 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 163714088464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(np_sample_cnt_q == '0)' has 1 failures:
35.adc_ctrl_stress_all_with_rand_reset.37561695494952761653344927763852147408015222935391482172451509769002833765922
Line 275, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest/run.log
Offending '(np_sample_cnt_q == '0)'
UVM_ERROR @ 4415715656 ps: (adc_ctrl_fsm.sv:386) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 4415715656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---