1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 21.000s | 0 | 1 | 0.00 | |
| V1 | smoke | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| V1 | csr_hw_reset | aes_csr_hw_reset | 34.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | aes_csr_rw | 47.000s | 2 | 20 | 10.00 | |
| V1 | csr_bit_bash | aes_csr_bit_bash | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 46.000s | 3 | 20 | 15.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 47.000s | 2 | 20 | 10.00 | |
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 6 | 106 | 5.66 | |||
| V2 | algorithm | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| aes_config_error | 46.000s | 6 | 50 | 12.00 | |||
| aes_stress | 47.000s | 2 | 50 | 4.00 | |||
| V2 | key_length | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| aes_config_error | 46.000s | 6 | 50 | 12.00 | |||
| aes_stress | 47.000s | 2 | 50 | 4.00 | |||
| V2 | back2back | aes_stress | 47.000s | 2 | 50 | 4.00 | |
| aes_b2b | 55.000s | 2 | 50 | 4.00 | |||
| V2 | backpressure | aes_stress | 47.000s | 2 | 50 | 4.00 | |
| V2 | multi_message | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| aes_config_error | 46.000s | 6 | 50 | 12.00 | |||
| aes_stress | 47.000s | 2 | 50 | 4.00 | |||
| aes_alert_reset | 43.000s | 4 | 50 | 8.00 | |||
| V2 | failure_test | aes_man_cfg_err | 50.000s | 4 | 50 | 8.00 | |
| aes_config_error | 46.000s | 6 | 50 | 12.00 | |||
| aes_alert_reset | 43.000s | 4 | 50 | 8.00 | |||
| V2 | trigger_clear_test | aes_clear | 54.000s | 2 | 50 | 4.00 | |
| V2 | nist_test_vectors | aes_nist_vectors | 20.000s | 0 | 1 | 0.00 | |
| V2 | reset_recovery | aes_alert_reset | 43.000s | 4 | 50 | 8.00 | |
| V2 | stress | aes_stress | 47.000s | 2 | 50 | 4.00 | |
| V2 | sideload | aes_stress | 47.000s | 2 | 50 | 4.00 | |
| aes_sideload | 42.000s | 2 | 50 | 4.00 | |||
| V2 | deinitialization | aes_deinit | 46.000s | 2 | 50 | 4.00 | |
| V2 | stress_all | aes_stress_all | 52.000s | 0 | 10 | 0.00 | |
| V2 | alert_test | aes_alert_test | 47.000s | 2 | 50 | 4.00 | |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 42.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_illegal_access | aes_tl_errors | 42.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 34.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 47.000s | 2 | 20 | 10.00 | |||
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 43.000s | 0 | 20 | 0.00 | |||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 34.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 47.000s | 2 | 20 | 10.00 | |||
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 43.000s | 0 | 20 | 0.00 | |||
| V2 | TOTAL | 27 | 501 | 5.39 | |||
| V2S | reseeding | aes_reseed | 46.000s | 6 | 50 | 12.00 | |
| V2S | fault_inject | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 42.000s | 1 | 20 | 5.00 | |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 42.000s | 1 | 20 | 5.00 | |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 42.000s | 1 | 20 | 5.00 | |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 42.000s | 1 | 20 | 5.00 | |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 42.000s | 0 | 20 | 0.00 | |
| V2S | tl_intg_err | aes_sec_cm | 42.000s | 0 | 5 | 0.00 | |
| aes_tl_intg_err | 42.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 42.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 43.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 42.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_main_config_sparse | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| aes_stress | 47.000s | 2 | 50 | 4.00 | |||
| aes_alert_reset | 43.000s | 4 | 50 | 8.00 | |||
| aes_core_fi | 56.000s | 1 | 70 | 1.43 | |||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 42.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_aux_config_regwen | aes_readability | 55.000s | 2 | 50 | 4.00 | |
| aes_stress | 47.000s | 2 | 50 | 4.00 | |||
| V2S | sec_cm_key_sideload | aes_stress | 47.000s | 2 | 50 | 4.00 | |
| aes_sideload | 42.000s | 2 | 50 | 4.00 | |||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 55.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 55.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_key_sec_wipe | aes_readability | 55.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 55.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 55.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 47.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_key_masking | aes_stress | 47.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| V2S | sec_cm_main_fsm_redun | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| aes_ctr_fi | 50.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_ctr_fi | 50.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_ctrl_sparse | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| aes_ctr_fi | 50.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 43.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| aes_ctr_fi | 50.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| aes_ctr_fi | 50.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_ctr_fi | 50.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 38.000s | 7 | 50 | 14.00 | |
| aes_control_fi | 56.000s | 12 | 300 | 4.00 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| V2S | TOTAL | 54 | 985 | 5.48 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 30.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 87 | 1602 | 5.43 |
Job returned non-zero exit code has 1513 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.107889571150334785488666562192182626756282385081871617883872553001228695524503
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_wake_up/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:25:41 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.55700009098707952949347144689039999773521475048859689940578615871618957063822
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_nist_vectors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:25:41 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_deinit has 48 failures.
0.aes_deinit.106661638322606898665745203470295225471972105643425565329933604626160021935243
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:25:42 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_deinit.111966225456072662312083642876587029377038032984727825823892442512688377130798
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:26:09 UTC (total: 00:00:33)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
Test aes_man_cfg_err has 46 failures.
0.aes_man_cfg_err.61479132643098407119440440485907705705848422229705053193863009679026748252301
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:25:52 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_man_cfg_err.114445395845338777656020536263994859087758489763559003573776585889165338915401
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:26:11 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 44 more failures.
Test aes_readability has 48 failures.
0.aes_readability.92961921645879099778591273490412661151064179015940651141105526631015927955298
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:25:43 UTC (total: 00:00:18)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_readability.10129534410570089975660461007953319186189632657536582192156259874510319633726
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:26:06 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
... and 27 more tests.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
5.aes_stress_all_with_rand_reset.113176855157737927313100330577456736607394081930770130109478905713346301634903
Line 517, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 420453258 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 420453258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
7.aes_stress_all_with_rand_reset.6696186414269059502643587062289525611209948377189883721309269326609998812685
Line 137, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 52658298 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 52658298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
[Errno *] No such file or directory: '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.txt' has 1 failures:
cov_report
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.log
[Errno 2] No such file or directory: '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.txt'