1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 55.000s | 0 | 1 | 0.00 | |
| V1 | smoke | aes_smoke | 51.000s | 4 | 50 | 8.00 | |
| V1 | csr_hw_reset | aes_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | aes_csr_rw | 54.000s | 0 | 20 | 0.00 | |
| V1 | csr_bit_bash | aes_csr_bit_bash | 33.000s | 1 | 5 | 20.00 | |
| V1 | csr_aliasing | aes_csr_aliasing | 30.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 38.000s | 0 | 20 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 54.000s | 0 | 20 | 0.00 | |
| aes_csr_aliasing | 30.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 5 | 106 | 4.72 | |||
| V2 | algorithm | aes_smoke | 51.000s | 4 | 50 | 8.00 | |
| aes_config_error | 47.000s | 5 | 50 | 10.00 | |||
| aes_stress | 1.000m | 1 | 50 | 2.00 | |||
| V2 | key_length | aes_smoke | 51.000s | 4 | 50 | 8.00 | |
| aes_config_error | 47.000s | 5 | 50 | 10.00 | |||
| aes_stress | 1.000m | 1 | 50 | 2.00 | |||
| V2 | back2back | aes_stress | 1.000m | 1 | 50 | 2.00 | |
| aes_b2b | 51.000s | 4 | 50 | 8.00 | |||
| V2 | backpressure | aes_stress | 1.000m | 1 | 50 | 2.00 | |
| V2 | multi_message | aes_smoke | 51.000s | 4 | 50 | 8.00 | |
| aes_config_error | 47.000s | 5 | 50 | 10.00 | |||
| aes_stress | 1.000m | 1 | 50 | 2.00 | |||
| aes_alert_reset | 43.000s | 3 | 50 | 6.00 | |||
| V2 | failure_test | aes_man_cfg_err | 55.000s | 6 | 50 | 12.00 | |
| aes_config_error | 47.000s | 5 | 50 | 10.00 | |||
| aes_alert_reset | 43.000s | 3 | 50 | 6.00 | |||
| V2 | trigger_clear_test | aes_clear | 43.000s | 1 | 50 | 2.00 | |
| V2 | nist_test_vectors | aes_nist_vectors | 50.000s | 0 | 1 | 0.00 | |
| V2 | reset_recovery | aes_alert_reset | 43.000s | 3 | 50 | 6.00 | |
| V2 | stress | aes_stress | 1.000m | 1 | 50 | 2.00 | |
| V2 | sideload | aes_stress | 1.000m | 1 | 50 | 2.00 | |
| aes_sideload | 42.000s | 5 | 50 | 10.00 | |||
| V2 | deinitialization | aes_deinit | 51.000s | 5 | 50 | 10.00 | |
| V2 | stress_all | aes_stress_all | 33.000s | 302.776us | 2 | 10 | 20.00 |
| V2 | alert_test | aes_alert_test | 42.000s | 2 | 50 | 4.00 | |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 38.000s | 2 | 20 | 10.00 | |
| V2 | tl_d_illegal_access | aes_tl_errors | 38.000s | 2 | 20 | 10.00 | |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 54.000s | 0 | 20 | 0.00 | |||
| aes_csr_aliasing | 30.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 46.000s | 2 | 20 | 10.00 | |||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 54.000s | 0 | 20 | 0.00 | |||
| aes_csr_aliasing | 30.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 46.000s | 2 | 20 | 10.00 | |||
| V2 | TOTAL | 38 | 501 | 7.58 | |||
| V2S | reseeding | aes_reseed | 50.000s | 2 | 50 | 4.00 | |
| V2S | fault_inject | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 54.000s | 0 | 20 | 0.00 | |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 54.000s | 0 | 20 | 0.00 | |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 54.000s | 0 | 20 | 0.00 | |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 54.000s | 0 | 20 | 0.00 | |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 43.000s | 0 | 20 | 0.00 | |
| V2S | tl_intg_err | aes_sec_cm | 46.000s | 0 | 5 | 0.00 | |
| aes_tl_intg_err | 54.000s | 0 | 20 | 0.00 | |||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 54.000s | 0 | 20 | 0.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 43.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 54.000s | 0 | 20 | 0.00 | |
| V2S | sec_cm_main_config_sparse | aes_smoke | 51.000s | 4 | 50 | 8.00 | |
| aes_stress | 1.000m | 1 | 50 | 2.00 | |||
| aes_alert_reset | 43.000s | 3 | 50 | 6.00 | |||
| aes_core_fi | 46.000s | 9 | 70 | 12.86 | |||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 54.000s | 0 | 20 | 0.00 | |
| V2S | sec_cm_aux_config_regwen | aes_readability | 43.000s | 1 | 50 | 2.00 | |
| aes_stress | 1.000m | 1 | 50 | 2.00 | |||
| V2S | sec_cm_key_sideload | aes_stress | 1.000m | 1 | 50 | 2.00 | |
| aes_sideload | 42.000s | 5 | 50 | 10.00 | |||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_key_sec_wipe | aes_readability | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 1.000m | 1 | 50 | 2.00 | |
| V2S | sec_cm_key_masking | aes_stress | 1.000m | 1 | 50 | 2.00 | |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| V2S | sec_cm_main_fsm_redun | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| aes_ctr_fi | 49.000s | 5 | 50 | 10.00 | |||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_ctr_fi | 49.000s | 5 | 50 | 10.00 | |||
| V2S | sec_cm_ctrl_sparse | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| aes_ctr_fi | 49.000s | 5 | 50 | 10.00 | |||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 43.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| aes_ctr_fi | 49.000s | 5 | 50 | 10.00 | |||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| aes_ctr_fi | 49.000s | 5 | 50 | 10.00 | |||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_ctr_fi | 49.000s | 5 | 50 | 10.00 | |||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 42.000s | 5 | 50 | 10.00 | |
| aes_control_fi | 47.000s | 14 | 300 | 4.67 | |||
| aes_cipher_fi | 51.000s | 21 | 350 | 6.00 | |||
| V2S | TOTAL | 57 | 985 | 5.79 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 51.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 100 | 1602 | 6.24 |
Job returned non-zero exit code has 1495 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.14232747523425891802370721620083400649740536146799567067234559081256550408490
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_wake_up/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:06:44 UTC (total: 00:00:55)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.57635106856817781413333900064138704312350109419820637748415927677298688726112
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_nist_vectors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:06:39 UTC (total: 00:00:50)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_deinit has 45 failures.
0.aes_deinit.114535578199579756927582543407660547809522056953676567217067879542398702877577
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:06:39 UTC (total: 00:00:50)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_deinit.44519940170929237713775725727510877852396382214122253670527103884190292085272
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:06:46 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 43 more failures.
Test aes_man_cfg_err has 44 failures.
0.aes_man_cfg_err.111068893838409618009553719596645418494420453931308211314556716787881327465413
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:06:44 UTC (total: 00:00:55)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_man_cfg_err.95223705933685095859444309747033675289043692852549739476649371414273869452232
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:06:43 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 42 more failures.
Test aes_readability has 49 failures.
0.aes_readability.35103483170383135466216175921337841943272923874887546919382865772981719781536
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:06:32 UTC (total: 00:00:43)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_readability.43712865226720711468005364446139016392257662042257376611458471039206472930602
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:06:47 UTC (total: 00:00:25)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
... and 27 more tests.
Job timed out after * minutes has 5 failures:
Test aes_control_fi has 2 failures.
0.aes_control_fi.113480513970330708329438657275076808907557654632353981485117802395482455228379
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
Job timed out after 1 minutes
213.aes_control_fi.45987757285914164896053547854999874479107942827865443321032874880033762504597
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/213.aes_control_fi/latest/run.log
Job timed out after 1 minutes
Test aes_cipher_fi has 3 failures.
0.aes_cipher_fi.46423860908501877217407127148596890983314030011785530894584347903606832088815
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
Job timed out after 1 minutes
9.aes_cipher_fi.47446449323897336466705805167023880377002331120454685661958117766983033523398
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
Job timed out after 1 minutes
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:946) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
2.aes_stress_all_with_rand_reset.33045812045280946639449695940804756982663001079693699870507935659058988341440
Line 175, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2157270881 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2157270881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
54.aes_control_fi.78347731127286552850989791983874624309484722770986025121175256794360971121301
Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/54.aes_control_fi/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
[Errno *] No such file or directory: '/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_report/cov_report.txt' has 1 failures:
cov_report
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_report/cov_report.log
[Errno 2] No such file or directory: '/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_report/cov_report.txt'