1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 42.000s | 4 | 50 | 8.00 | |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 30.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | csrng_csr_rw | 38.000s | 1 | 20 | 5.00 | |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | csrng_csr_aliasing | 29.000s | 1 | 5 | 20.00 | |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 38.000s | 0 | 20 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 38.000s | 1 | 20 | 5.00 | |
| csrng_csr_aliasing | 29.000s | 1 | 5 | 20.00 | |||
| V1 | TOTAL | 6 | 105 | 5.71 | |||
| V2 | interrupts | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| V2 | alerts | csrng_alert | 51.000s | 21 | 500 | 4.20 | |
| V2 | err | csrng_err | 54.000s | 17 | 500 | 3.40 | |
| V2 | cmds | csrng_cmds | 2.850m | 12.104ms | 1 | 50 | 2.00 |
| V2 | life cycle | csrng_cmds | 2.850m | 12.104ms | 1 | 50 | 2.00 |
| V2 | stress_all | csrng_stress_all | 6.983m | 29.713ms | 3 | 50 | 6.00 |
| V2 | intr_test | csrng_intr_test | 46.000s | 3 | 50 | 6.00 | |
| V2 | alert_test | csrng_alert_test | 47.000s | 1 | 50 | 2.00 | |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 55.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_illegal_access | csrng_tl_errors | 55.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 30.000s | 0 | 5 | 0.00 | |
| csrng_csr_rw | 38.000s | 1 | 20 | 5.00 | |||
| csrng_csr_aliasing | 29.000s | 1 | 5 | 20.00 | |||
| csrng_same_csr_outstanding | 38.000s | 0 | 20 | 0.00 | |||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 30.000s | 0 | 5 | 0.00 | |
| csrng_csr_rw | 38.000s | 1 | 20 | 5.00 | |||
| csrng_csr_aliasing | 29.000s | 1 | 5 | 20.00 | |||
| csrng_same_csr_outstanding | 38.000s | 0 | 20 | 0.00 | |||
| V2 | TOTAL | 62 | 1440 | 4.31 | |||
| V2S | tl_intg_err | csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |
| csrng_tl_intg_err | 46.000s | 2 | 20 | 10.00 | |||
| V2S | sec_cm_config_regwen | csrng_regwen | 43.000s | 1 | 50 | 2.00 | |
| csrng_csr_rw | 38.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_config_mubi | csrng_alert | 51.000s | 21 | 500 | 4.20 | |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 6.983m | 29.713ms | 3 | 50 | 6.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 51.000s | 21 | 500 | 4.20 | |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 6.983m | 29.713ms | 3 | 50 | 6.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 51.000s | 21 | 500 | 4.20 | |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 46.000s | 2 | 20 | 10.00 | |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| csrng_sec_cm | 30.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 51.000s | 16 | 200 | 8.00 | |
| csrng_err | 54.000s | 17 | 500 | 3.40 | |||
| V2S | TOTAL | 3 | 75 | 4.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 38.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 71 | 1630 | 4.36 |
Job returned non-zero exit code has 1557 failures:
0.csrng_smoke.82475917344974985727752898420508273040786232705666959262022361131929075802621
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:26 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_smoke.41560223857641173980951202068765116176651232764401819006806581582326993530078
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:30 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 44 more failures.
0.csrng_cmds.86724650457453320559754519673440882089140550782393828929381753175592772186587
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:44 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_cmds.99672858354894182732780723285674235341776403271648683996712960215662595797107
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_cmds/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:49 UTC (total: 00:00:39)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
0.csrng_stress_all.73541173746373157034269640294953285084299187419121401625688968215001712282273
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:27 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
2.csrng_stress_all.100399464917743272695873028371891219803685937586745906689665152511734264380869
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:42 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.csrng_alert.61263913313111656382420947444947751468565211413431130497214366992276992612439
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:36 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_alert.69487352311112172484759705148702507292633014014223196303951959899238589738338
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:31 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 477 more failures.
0.csrng_err.96067893960870655731618787786915379972151645122463004139498869978804076755349
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:32 UTC (total: 00:00:26)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_err.87726042274956329017121100635244465276956276216289043791430972910211447982729
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 09:39:41 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 479 more failures.
UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 2 failures:
142.csrng_err.72558393854801363904660264679153524201719362329762771456780289940991657047676
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/142.csrng_err/latest/run.log
UVM_FATAL @ 5838892 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
----| PATH NOT FOUND
UVM_INFO @ 5838892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
497.csrng_err.14583900559241476716924306901845574063889184684076917510691740739798859668822
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/497.csrng_err/latest/run.log
UVM_FATAL @ 2343012 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
----| PATH NOT FOUND
UVM_INFO @ 2343012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
[Errno *] No such file or directory: '/nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.txt' has 1 failures:
cov_report
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.log
[Errno 2] No such file or directory: '/nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.txt'