EDN Simulation Results

Sunday September 21 2025 01:07:51 UTC

GitHub Revision: 1a5d173

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 30.729s 46 50 92.00
V1 csr_hw_reset edn_csr_hw_reset 0.740s 30.373us 5 5 100.00
V1 csr_rw edn_csr_rw 19.970s 17 20 85.00
V1 csr_bit_bash edn_csr_bit_bash 3.900s 916.460us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.200s 154.358us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 22.069s 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 19.970s 17 20 85.00
edn_csr_aliasing 1.200s 154.358us 5 5 100.00
V1 TOTAL 96 105 91.43
V2 firmware edn_genbits 1.776m 14.558ms 274 300 91.33
V2 csrng_commands edn_genbits 1.776m 14.558ms 274 300 91.33
V2 genbits edn_genbits 1.776m 14.558ms 274 300 91.33
V2 interrupts edn_intr 32.948s 48 50 96.00
V2 alerts edn_alert 28.456s 187 200 93.50
V2 errs edn_err 24.793s 95 100 95.00
V2 disable edn_disable 15.946s 49 50 98.00
edn_disable_auto_req_mode 26.103s 47 50 94.00
V2 stress_all edn_stress_all 20.280s 49 50 98.00
V2 intr_test edn_intr_test 26.227s 47 50 94.00
V2 alert_test edn_alert_test 24.549s 44 50 88.00
V2 tl_d_oob_addr_access edn_tl_errors 3.120s 439.684us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.120s 439.684us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.740s 30.373us 5 5 100.00
edn_csr_rw 19.970s 17 20 85.00
edn_csr_aliasing 1.200s 154.358us 5 5 100.00
edn_same_csr_outstanding 15.935s 19 20 95.00
V2 tl_d_partial_access edn_csr_hw_reset 0.740s 30.373us 5 5 100.00
edn_csr_rw 19.970s 17 20 85.00
edn_csr_aliasing 1.200s 154.358us 5 5 100.00
edn_same_csr_outstanding 15.935s 19 20 95.00
V2 TOTAL 879 940 93.51
V2S tl_intg_err edn_sec_cm 16.281s 4 5 80.00
edn_tl_intg_err 26.633s 15 20 75.00
V2S sec_cm_config_regwen edn_regwen 0.840s 19.497us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 28.456s 187 200 93.50
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 16.281s 4 5 80.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 16.281s 4 5 80.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 16.281s 4 5 80.00
V2S sec_cm_ctr_redun edn_sec_cm 16.281s 4 5 80.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 28.456s 187 200 93.50
edn_sec_cm 16.281s 4 5 80.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 28.456s 187 200 93.50
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 26.633s 15 20 75.00
V2S TOTAL 29 35 82.86
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.486m 16.346ms 29 50 58.00
V3 TOTAL 29 50 58.00
TOTAL 1033 1130 91.42

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.58 98.87 94.29 97.02 91.86 96.33 97.56 93.13

Failure Buckets