1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 41.304s | 7 | 10 | 70.00 | |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.760s | 29.144us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.790s | 35.141us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 10.690s | 3.144ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 22.136s | 3 | 5 | 60.00 | |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 1.020m | 9.199ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.790s | 35.141us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 22.136s | 3 | 5 | 60.00 | |||
| V1 | TOTAL | 60 | 65 | 92.31 | |||
| V2 | long_msg | hmac_long_msg | 1.158m | 5.752ms | 10 | 10 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.249m | 3.601ms | 23 | 25 | 92.00 |
| V2 | test_vectors | hmac_test_sha256_vectors | 3.505m | 28.737ms | 29 | 30 | 96.67 |
| hmac_test_sha384_vectors | 7.760m | 16.671ms | 64 | 75 | 85.33 | ||
| hmac_test_sha512_vectors | 7.093m | 56.737ms | 66 | 75 | 88.00 | ||
| hmac_test_hmac256_vectors | 24.558s | 42 | 50 | 84.00 | |||
| hmac_test_hmac384_vectors | 22.318s | 52 | 60 | 86.67 | |||
| hmac_test_hmac512_vectors | 47.313s | 66 | 75 | 88.00 | |||
| V2 | burst_wr | hmac_burst_wr | 26.730s | 698.356us | 43 | 50 | 86.00 |
| V2 | datapath_stress | hmac_datapath_stress | 12.436m | 20.195ms | 10 | 10 | 100.00 |
| V2 | error | hmac_error | 1.608m | 21.660ms | 10 | 10 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.198m | 7.652ms | 9 | 10 | 90.00 |
| V2 | save_and_restore | hmac_smoke | 41.304s | 7 | 10 | 70.00 | |
| hmac_long_msg | 1.158m | 5.752ms | 10 | 10 | 100.00 | ||
| hmac_back_pressure | 1.249m | 3.601ms | 23 | 25 | 92.00 | ||
| hmac_datapath_stress | 12.436m | 20.195ms | 10 | 10 | 100.00 | ||
| hmac_burst_wr | 26.730s | 698.356us | 43 | 50 | 86.00 | ||
| hmac_stress_all | 28.954m | 31.948ms | 43 | 50 | 86.00 | ||
| V2 | fifo_empty_status_interrupt | hmac_smoke | 41.304s | 7 | 10 | 70.00 | |
| hmac_long_msg | 1.158m | 5.752ms | 10 | 10 | 100.00 | ||
| hmac_back_pressure | 1.249m | 3.601ms | 23 | 25 | 92.00 | ||
| hmac_datapath_stress | 12.436m | 20.195ms | 10 | 10 | 100.00 | ||
| hmac_wipe_secret | 1.198m | 7.652ms | 9 | 10 | 90.00 | ||
| hmac_test_sha256_vectors | 3.505m | 28.737ms | 29 | 30 | 96.67 | ||
| hmac_test_sha384_vectors | 7.760m | 16.671ms | 64 | 75 | 85.33 | ||
| hmac_test_sha512_vectors | 7.093m | 56.737ms | 66 | 75 | 88.00 | ||
| hmac_test_hmac256_vectors | 24.558s | 42 | 50 | 84.00 | |||
| hmac_test_hmac384_vectors | 22.318s | 52 | 60 | 86.67 | |||
| hmac_test_hmac512_vectors | 47.313s | 66 | 75 | 88.00 | |||
| V2 | wide_digest_configurable_key_length | hmac_smoke | 41.304s | 7 | 10 | 70.00 | |
| hmac_long_msg | 1.158m | 5.752ms | 10 | 10 | 100.00 | ||
| hmac_back_pressure | 1.249m | 3.601ms | 23 | 25 | 92.00 | ||
| hmac_datapath_stress | 12.436m | 20.195ms | 10 | 10 | 100.00 | ||
| hmac_burst_wr | 26.730s | 698.356us | 43 | 50 | 86.00 | ||
| hmac_error | 1.608m | 21.660ms | 10 | 10 | 100.00 | ||
| hmac_wipe_secret | 1.198m | 7.652ms | 9 | 10 | 90.00 | ||
| hmac_test_sha256_vectors | 3.505m | 28.737ms | 29 | 30 | 96.67 | ||
| hmac_test_sha384_vectors | 7.760m | 16.671ms | 64 | 75 | 85.33 | ||
| hmac_test_sha512_vectors | 7.093m | 56.737ms | 66 | 75 | 88.00 | ||
| hmac_test_hmac256_vectors | 24.558s | 42 | 50 | 84.00 | |||
| hmac_test_hmac384_vectors | 22.318s | 52 | 60 | 86.67 | |||
| hmac_test_hmac512_vectors | 47.313s | 66 | 75 | 88.00 | |||
| hmac_stress_all | 28.954m | 31.948ms | 43 | 50 | 86.00 | ||
| V2 | stress_all | hmac_stress_all | 28.954m | 31.948ms | 43 | 50 | 86.00 |
| V2 | alert_test | hmac_alert_test | 22.281s | 43 | 50 | 86.00 | |
| V2 | intr_test | hmac_intr_test | 23.958s | 47 | 50 | 94.00 | |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 18.019s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | hmac_tl_errors | 18.019s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.760s | 29.144us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.790s | 35.141us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 22.136s | 3 | 5 | 60.00 | |||
| hmac_same_csr_outstanding | 1.820s | 429.779us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.760s | 29.144us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.790s | 35.141us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 22.136s | 3 | 5 | 60.00 | |||
| hmac_same_csr_outstanding | 1.820s | 429.779us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 595 | 670 | 88.81 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.860s | 193.018us | 4 | 5 | 80.00 |
| hmac_tl_intg_err | 3.150s | 1.126ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 3.150s | 1.126ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 41.304s | 7 | 10 | 70.00 | |
| V3 | stress_reset | hmac_stress_reset | 22.271s | 23 | 25 | 92.00 | |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 5.911m | 9.054ms | 32 | 35 | 91.43 |
| V3 | TOTAL | 55 | 60 | 91.67 | |||
| Unmapped tests | hmac_directed | 15.953s | 0 | 1 | 0.00 | ||
| TOTAL | 734 | 821 | 89.40 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.34 | 99.95 | 96.85 | 100.00 | 94.12 | 99.83 | 97.61 | 100.00 |
Job returned non-zero exit code has 80 failures:
Test hmac_smoke has 3 failures.
0.hmac_smoke.68436745174376909874908750401205901807359825095461094788707209175410285829835
Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 11:41 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
2.hmac_smoke.61721202743592854475440459937098955940345564717354130770155037650689687451672
Log /nightly/current_run/scratch/master/hmac-sim-vcs/2.hmac_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 11:42 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test hmac_directed has 1 failures.
0.hmac_directed.69229372409661877099894585923064736621056290960882015364457083853246499450427
Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_directed/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 11:42 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test hmac_intr_test has 3 failures.
1.hmac_intr_test.26252878027211531264181308330698326313953759145723352791372008236585917728637
Log /nightly/current_run/scratch/master/hmac-sim-vcs/1.hmac_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:25 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
15.hmac_intr_test.62742737319784680311130203312610650866961260163011485165883127080013118125478
Log /nightly/current_run/scratch/master/hmac-sim-vcs/15.hmac_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:26 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test hmac_csr_aliasing has 2 failures.
1.hmac_csr_aliasing.3522766839564689321393859794315927250043996322716839232162714742370480432487
Log /nightly/current_run/scratch/master/hmac-sim-vcs/1.hmac_csr_aliasing/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:25 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
2.hmac_csr_aliasing.35948650781819702289230954083609347678774583486847303038924468286313589034405
Log /nightly/current_run/scratch/master/hmac-sim-vcs/2.hmac_csr_aliasing/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 12:26 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test hmac_test_sha384_vectors has 11 failures.
2.hmac_test_sha384_vectors.52985975037653581672034257167112949260852571301792386798388649454405659121921
Log /nightly/current_run/scratch/master/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 11:42 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
7.hmac_test_sha384_vectors.68389961221984897467717293854629729268806188960756563005444581600419388894781
Log /nightly/current_run/scratch/master/hmac-sim-vcs/7.hmac_test_sha384_vectors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 11:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 9 more failures.
... and 13 more tests.
Job timed out after * minutes has 7 failures:
Test hmac_sec_cm has 1 failures.
3.hmac_sec_cm.69940200802487406369365721090690596077505562730049841334613128502285984301421
Log /nightly/current_run/scratch/master/hmac-sim-vcs/3.hmac_sec_cm/latest/run.log
Job timed out after 60 minutes
Test hmac_stress_all_with_rand_reset has 1 failures.
24.hmac_stress_all_with_rand_reset.78256617497087684869983188236379522562199930069400949164087858935596387360464
Log /nightly/current_run/scratch/master/hmac-sim-vcs/24.hmac_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
Test hmac_alert_test has 1 failures.
32.hmac_alert_test.108277946880641464699339252247551653634109739370336137921506617823492454343769
Log /nightly/current_run/scratch/master/hmac-sim-vcs/32.hmac_alert_test/latest/run.log
Job timed out after 60 minutes
Test hmac_test_hmac512_vectors has 2 failures.
33.hmac_test_hmac512_vectors.2455991237557230301397815984176500959822953943273788589673537290718044814430
Log /nightly/current_run/scratch/master/hmac-sim-vcs/33.hmac_test_hmac512_vectors/latest/run.log
Job timed out after 60 minutes
63.hmac_test_hmac512_vectors.92334366619795937171758455571733237996686726366199167549926770874411753536402
Log /nightly/current_run/scratch/master/hmac-sim-vcs/63.hmac_test_hmac512_vectors/latest/run.log
Job timed out after 60 minutes
Test hmac_test_hmac256_vectors has 1 failures.
48.hmac_test_hmac256_vectors.103630491396156119868660543480752002340624227342537723168274910683735509234827
Log /nightly/current_run/scratch/master/hmac-sim-vcs/48.hmac_test_hmac256_vectors/latest/run.log
Job timed out after 60 minutes
... and 1 more tests.