1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 22.603s | 46 | 50 | 92.00 | |
| V1 | random | keymgr_random | 37.140s | 31.434ms | 47 | 50 | 94.00 |
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.070s | 58.941us | 5 | 5 | 100.00 |
| V1 | csr_rw | keymgr_csr_rw | 15.796s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 23.842s | 4 | 5 | 80.00 | |
| V1 | csr_aliasing | keymgr_csr_aliasing | 26.173s | 4 | 5 | 80.00 | |
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 17.885s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 15.796s | 19 | 20 | 95.00 | |
| keymgr_csr_aliasing | 26.173s | 4 | 5 | 80.00 | |||
| V1 | TOTAL | 143 | 155 | 92.26 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 1.012m | 2.212ms | 49 | 50 | 98.00 |
| V2 | sideload | keymgr_sideload | 28.110s | 6.866ms | 48 | 50 | 96.00 |
| keymgr_sideload_kmac | 27.050s | 13.913ms | 47 | 50 | 94.00 | ||
| keymgr_sideload_aes | 28.090s | 1.381ms | 46 | 50 | 92.00 | ||
| keymgr_sideload_otbn | 35.610s | 5.862ms | 44 | 50 | 88.00 | ||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 22.343s | 47 | 50 | 94.00 | |
| V2 | lc_disable | keymgr_lc_disable | 21.710s | 2.570ms | 47 | 50 | 94.00 |
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 34.794s | 47 | 50 | 94.00 | |
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 35.130s | 9.198ms | 47 | 50 | 94.00 |
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 20.443s | 45 | 50 | 90.00 | |
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 26.608s | 43 | 50 | 86.00 | |
| V2 | stress_all | keymgr_stress_all | 1.900m | 5.828ms | 43 | 50 | 86.00 |
| V2 | intr_test | keymgr_intr_test | 26.273s | 49 | 50 | 98.00 | |
| V2 | alert_test | keymgr_alert_test | 0.900s | 22.477us | 48 | 50 | 96.00 |
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 20.412s | 17 | 20 | 85.00 | |
| V2 | tl_d_illegal_access | keymgr_tl_errors | 20.412s | 17 | 20 | 85.00 | |
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.070s | 58.941us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 15.796s | 19 | 20 | 95.00 | |||
| keymgr_csr_aliasing | 26.173s | 4 | 5 | 80.00 | |||
| keymgr_same_csr_outstanding | 22.503s | 19 | 20 | 95.00 | |||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.070s | 58.941us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 15.796s | 19 | 20 | 95.00 | |||
| keymgr_csr_aliasing | 26.173s | 4 | 5 | 80.00 | |||
| keymgr_same_csr_outstanding | 22.503s | 19 | 20 | 95.00 | |||
| V2 | TOTAL | 686 | 740 | 92.70 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | tl_intg_err | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| keymgr_tl_intg_err | 15.967s | 19 | 20 | 95.00 | |||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 3.730s | 390.513us | 19 | 20 | 95.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 3.730s | 390.513us | 19 | 20 | 95.00 |
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 3.730s | 390.513us | 19 | 20 | 95.00 |
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 3.730s | 390.513us | 19 | 20 | 95.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 32.987s | 18 | 20 | 90.00 | |
| V2S | prim_count_check | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | prim_fsm_check | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 15.967s | 19 | 20 | 95.00 | |
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 3.730s | 390.513us | 19 | 20 | 95.00 |
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.012m | 2.212ms | 49 | 50 | 98.00 |
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 37.140s | 31.434ms | 47 | 50 | 94.00 |
| keymgr_csr_rw | 15.796s | 19 | 20 | 95.00 | |||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 37.140s | 31.434ms | 47 | 50 | 94.00 |
| keymgr_csr_rw | 15.796s | 19 | 20 | 95.00 | |||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 37.140s | 31.434ms | 47 | 50 | 94.00 |
| keymgr_csr_rw | 15.796s | 19 | 20 | 95.00 | |||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 21.710s | 2.570ms | 47 | 50 | 94.00 |
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 20.443s | 45 | 50 | 90.00 | |
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 20.443s | 45 | 50 | 90.00 | |
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 37.140s | 31.434ms | 47 | 50 | 94.00 |
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 16.033s | 47 | 50 | 94.00 | |
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 16.304s | 47 | 50 | 94.00 | |
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 21.710s | 2.570ms | 47 | 50 | 94.00 |
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 16.304s | 47 | 50 | 94.00 | |
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 16.304s | 47 | 50 | 94.00 | |
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 16.304s | 47 | 50 | 94.00 | |
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 22.412s | 2 | 5 | 40.00 | |
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 16.304s | 47 | 50 | 94.00 | |
| V2S | TOTAL | 152 | 165 | 92.12 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 30.888s | 27 | 50 | 54.00 | |
| V3 | TOTAL | 27 | 50 | 54.00 | |||
| TOTAL | 1008 | 1110 | 90.81 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.65 | 99.13 | 98.15 | 98.35 | 100.00 | 99.01 | 97.71 | 91.16 |
Job returned non-zero exit code has 66 failures:
Test keymgr_sideload_aes has 2 failures.
0.keymgr_sideload_aes.20723215037218266146001403240513754089992964090998989088822384172634040483435
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_aes/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:07 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
31.keymgr_sideload_aes.57067249095500218651608415672023845457662367239526593414349245831453484793764
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/31.keymgr_sideload_aes/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:19 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test keymgr_random has 3 failures.
0.keymgr_random.42352205955929946340035926277298247168245171855812021782064616900413977661616
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_random/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:07 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
9.keymgr_random.79558395959930577869294739100086100965737140590381177304298639180333398073927
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_random/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:13 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test keymgr_kmac_rsp_err has 2 failures.
0.keymgr_kmac_rsp_err.10037994249056831661360528886152635752602716406962267398238852165623248653524
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:08 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
38.keymgr_kmac_rsp_err.102712714522645141545067217309588726997485774977515072402233813904623662417922
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:20 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test keymgr_sec_cm has 3 failures.
0.keymgr_sec_cm.96366760852284635474736934674827617938592907358507521939849178597811116768602
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sec_cm/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:08 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
1.keymgr_sec_cm.110038820012991329313990868355497341064030026154183715611847605706773605042410
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_sec_cm/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:09 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test keymgr_shadow_reg_errors_with_csr_rw has 2 failures.
0.keymgr_shadow_reg_errors_with_csr_rw.69807580474546442994683814783152191050652073767924781618561718377079337115459
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:52 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
13.keymgr_shadow_reg_errors_with_csr_rw.75328715200757368742581404738113950717635887686923948691680117423916191872756
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:53 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 21 more tests.
UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
0.keymgr_stress_all_with_rand_reset.63325651799747064871195884213559017101676465956862853277168219808629930990015
Line 199, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 408518897 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 408518897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_stress_all_with_rand_reset.81461225064770598479485208611222186895878837252504430237007582079735853788424
Line 211, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 127079895 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 127079895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
Job timed out after * minutes has 12 failures:
Test keymgr_sideload_protect has 1 failures.
1.keymgr_sideload_protect.57287633874353802189571124803760183871442353334016207287754695313921423762420
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_sideload_protect/latest/run.log
Job timed out after 60 minutes
Test keymgr_alert_test has 2 failures.
1.keymgr_alert_test.1280581748561270754630229543183426455251855029760062983677985243054364362522
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_alert_test/latest/run.log
Job timed out after 60 minutes
6.keymgr_alert_test.108016813366041492632377643992199606160888135336481219689880700608263388702268
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_alert_test/latest/run.log
Job timed out after 60 minutes
Test keymgr_tl_errors has 1 failures.
5.keymgr_tl_errors.70197903574681851002411002006369264874884236497605060402761938820695630831927
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/5.keymgr_tl_errors/latest/run.log
Job timed out after 60 minutes
Test keymgr_cfg_regwen has 1 failures.
7.keymgr_cfg_regwen.97933092834343029268333688082649797173252426581214307677011945260009017115357
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest/run.log
Job timed out after 60 minutes
Test keymgr_lc_disable has 2 failures.
7.keymgr_lc_disable.90296581448764219887677260090350325401983698133277093950183106443450707297736
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_lc_disable/latest/run.log
Job timed out after 60 minutes
29.keymgr_lc_disable.99441744941050399021648592169777490200927807923127437299434531388700495365305
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_lc_disable/latest/run.log
Job timed out after 60 minutes
... and 5 more tests.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
Test keymgr_sync_async_fault_cross has 1 failures.
24.keymgr_sync_async_fault_cross.11443850072101378258974466730932913402713454373889809967645002277267256563512
Line 86, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 3580250 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 3580250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sideload_aes has 1 failures.
30.keymgr_sideload_aes.15158109113408226012248809103433087697604417795470111041838629945227161105202
Line 111, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/30.keymgr_sideload_aes/latest/run.log
UVM_ERROR @ 49981747 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 49981747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 1 failures.
43.keymgr_stress_all.84355372017829256937141547300328031248112427008464260771410632329657950833897
Line 1516, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_stress_all/latest/run.log
UVM_ERROR @ 221914543 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 221914543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
30.keymgr_kmac_rsp_err.3017983138923169643280600412812107092768923634544797474619120609244150089575
Line 115, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 19432798 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 19432798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Sealing Kmac has 1 failures:
47.keymgr_stress_all.30195233603927570842255317904702764291819551812355107282547734241786525610662
Line 849, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log
UVM_ERROR @ 784423521 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10152038779274008324342333204308600481200552457726762781527630599169397984351912441774545632964623348903984422489938075751096056146143047352410127731160235 [0xc1d621c375dfab764f9ddce600242722c6df29974f05132a52d70a84a745f25203ebe0085bb8e6048830846af8e08b08e7abd9024e3d1b014c5ca55e876674ab] vs 10152038779274008324342333204308600481200552457726762781527630599169397984351912441774545632964623348903984422489938075751096056146143047352410127731160235 [0xc1d621c375dfab764f9ddce600242722c6df29974f05132a52d70a84a745f25203ebe0085bb8e6048830846af8e08b08e7abd9024e3d1b014c5ca55e876674ab]) KMAC key at state StDisabled for Sealing Kmac
UVM_INFO @ 784423521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---