1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 50.410s | 47.367ms | 45 | 50 | 90.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | kmac_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | kmac_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | kmac_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0 | 20 | 0.00 | ||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | kmac_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | kmac_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 45 | 115 | 39.13 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 38.905m | 367.523ms | 41 | 50 | 82.00 |
| V2 | burst_write | kmac_burst_write | 11.650m | 37.381ms | 44 | 50 | 88.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 29.390s | 2.306ms | 4 | 5 | 80.00 |
| kmac_test_vectors_sha3_256 | 25.683m | 943.274ms | 4 | 5 | 80.00 | ||
| kmac_test_vectors_sha3_384 | 17.498m | 64.324ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 13.057m | 99.703ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 26.545m | 142.391ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 17.149m | 34.967ms | 4 | 5 | 80.00 | ||
| kmac_test_vectors_kmac | 2.320s | 233.406us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 1.990s | 28.535us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 5.260m | 428.348ms | 37 | 50 | 74.00 |
| V2 | app | kmac_app | 3.805m | 72.300ms | 40 | 50 | 80.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 3.662m | 63.943ms | 5 | 10 | 50.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 3.505m | 58.865ms | 40 | 50 | 80.00 |
| V2 | error | kmac_error | 5.431m | 21.848ms | 44 | 50 | 88.00 |
| V2 | key_error | kmac_key_error | 29.002s | 43 | 50 | 86.00 | |
| V2 | sideload_invalid | kmac_sideload_invalid | 1.416m | 10.008ms | 30 | 50 | 60.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 24.440s | 1.421ms | 16 | 20 | 80.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 24.660s | 7.338ms | 14 | 20 | 70.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 39.031s | 5 | 10 | 50.00 | |
| V2 | lc_escalation | kmac_lc_escalation | 25.590s | 2.338ms | 38 | 50 | 76.00 |
| V2 | stress_all | kmac_stress_all | 33.699m | 303.438ms | 41 | 50 | 82.00 |
| V2 | intr_test | kmac_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | kmac_alert_test | 26.519s | 43 | 50 | 86.00 | |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | kmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| kmac_csr_rw | 0 | 20 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| kmac_csr_rw | 0 | 20 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 518 | 740 | 70.00 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | kmac_sec_cm | 50.570s | 43.300ms | 4 | 5 | 80.00 |
| kmac_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 25.590s | 2.338ms | 38 | 50 | 76.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 50.410s | 47.367ms | 45 | 50 | 90.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 5.260m | 428.348ms | 37 | 50 | 74.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 50.570s | 43.300ms | 4 | 5 | 80.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 50.570s | 43.300ms | 4 | 5 | 80.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 50.570s | 43.300ms | 4 | 5 | 80.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 50.410s | 47.367ms | 45 | 50 | 90.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 25.590s | 2.338ms | 38 | 50 | 76.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 50.570s | 43.300ms | 4 | 5 | 80.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 3.583m | 16.430ms | 8 | 10 | 80.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 50.410s | 47.367ms | 45 | 50 | 90.00 |
| V2S | TOTAL | 12 | 75 | 16.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 3.351m | 4.679ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 580 | 940 | 61.70 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.50 | 97.65 | 92.29 | 99.87 | 73.55 | 95.97 | 95.64 | 71.51 |
Job killed most likely because its dependent job failed. has 215 failures:
0.kmac_shadow_reg_errors.341483611049791376556619264426744202484296158815150072188970189836771282964
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log
1.kmac_shadow_reg_errors.4073226639388852622732007206223377727347488950428859092782710244244732875827
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log
... and 18 more failures.
0.kmac_shadow_reg_errors_with_csr_rw.91780868381294239710195196179016070805848917790461704628701659499693421911711
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
1.kmac_shadow_reg_errors_with_csr_rw.24428329212418826414622008802053048367411198894537035047932470290072839224078
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
... and 18 more failures.
0.kmac_mem_walk.67001142924930048060517168354530097862389393455655527365798751015049692706164
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest/run.log
1.kmac_mem_walk.80048998558218908699007974944914515157085558951287745073247897768939113981688
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest/run.log
... and 3 more failures.
0.kmac_mem_partial_access.95171346651642788210261663689747726602062120965968813929694904441102171195698
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest/run.log
1.kmac_mem_partial_access.85418329941811901434651126228147325349351671929199016704514330339844366218666
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest/run.log
... and 3 more failures.
0.kmac_tl_errors.44464046470701605863741373366136936648217708416842120408549720192401112278987
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest/run.log
1.kmac_tl_errors.71083317730176931340915094801038834789773425221967034931532901380594271287716
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest/run.log
... and 18 more failures.
Job returned non-zero exit code has 105 failures:
Test cover_reg_top has 1 failures.
cover_reg_top
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/build.log
recompiling module tb
All of 118 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 21.216 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test kmac_entropy_ready_error has 5 failures.
0.kmac_entropy_ready_error.9961578351970186015433610344650500410584788310343276161487838860243857733454
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:17 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
1.kmac_entropy_ready_error.112402613177491670239042349405336122831892483816492656051894200019301630512336
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:20 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
Test kmac_lc_escalation has 8 failures.
0.kmac_lc_escalation.46238233938102318254583737944967585723526899269835990839502324650797436741742
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:17 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
5.kmac_lc_escalation.96468017506011534914767505382653335586368677250243098600845684139113580243109
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:26 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 6 more failures.
Test kmac_mubi has 2 failures.
1.kmac_mubi.5990943770776105171521101860000847167826383509359009261264560100434431909856
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_mubi/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:19 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
6.kmac_mubi.31015829728338859258885491027222127566963000832420766716989002580425400477674
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/6.kmac_mubi/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:27 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_key_error has 4 failures.
1.kmac_key_error.40486056026202449485973870363554931824701722844974490063452458411292544155494
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_key_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:19 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
7.kmac_key_error.80939173229555569881739947869043329543608973715854226376390317319289293972315
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_key_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:30 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
... and 17 more tests.
Job timed out after * minutes has 24 failures:
Test kmac_test_vectors_sha3_256 has 1 failures.
2.kmac_test_vectors_sha3_256.76259522345877143389240073572905817630477943853059662299614315976954992057978
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest/run.log
Job timed out after 90 minutes
Test kmac_lc_escalation has 4 failures.
3.kmac_lc_escalation.284588064021844088644803689179234065737121624290638197296379066630461792348
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest/run.log
Job timed out after 60 minutes
36.kmac_lc_escalation.115562129605108250439523013154346569290380920724720266410659246692586168337584
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest/run.log
Job timed out after 60 minutes
... and 2 more failures.
Test kmac_entropy_refresh has 4 failures.
5.kmac_entropy_refresh.42312273956123552719255710984455652419048161709452470575778780136320486571097
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest/run.log
Job timed out after 60 minutes
7.kmac_entropy_refresh.80064329655326241424632593245638370039411118259232275362284457490310971764422
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest/run.log
Job timed out after 60 minutes
... and 2 more failures.
Test kmac_app_with_partial_data has 1 failures.
7.kmac_app_with_partial_data.7254240515640932829536361287286578622696716181220701732625687032068632909009
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest/run.log
Job timed out after 60 minutes
Test kmac_key_error has 2 failures.
8.kmac_key_error.68543307606394747786593028410780706065237389090915790000681843778669906612615
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_key_error/latest/run.log
Job timed out after 60 minutes
17.kmac_key_error.3655271380981507866887129289899494554653565181427210711593391710080384881213
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/17.kmac_key_error/latest/run.log
Job timed out after 60 minutes
... and 7 more tests.
UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
2.kmac_stress_all_with_rand_reset.68982649678927983948432347177390526569855517268073462153556315125454589531953
Line 159, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2331749748 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2331749748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_stress_all_with_rand_reset.11095788194825766469509274423031871923403388966983357067601278175588721066373
Line 392, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51610646472 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 51610646472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
8.kmac_sideload_invalid.17329367925419477026609564687587504454005944781899273987479424621251880043717
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10008351935 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa67c4000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008351935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.kmac_sideload_invalid.56140719315774908422568800036105141194449179978781498500746693977425694052973
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10011102076 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x51e60000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10011102076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
24.kmac_sideload_invalid.91448745290712985229182028248528165245411893648805013880380385194940331963744
Line 88, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 11285427474 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x73c06000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 11285427474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.kmac_sideload_invalid.10464651283086902010211656147966481400778197643770750205911164236735143181355
Line 86, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/47.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10198768105 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x86908000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10198768105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:525) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
8.kmac_stress_all_with_rand_reset.108768119148833451283495129504657609168348707285323012809780506524668451435217
Line 404, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6202006129 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 6202006129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
10.kmac_sideload_invalid.25023915086544198744264691022694412503093910383643840012741322505310062874981
Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10055050396 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x59a89000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10055050396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
19.kmac_key_error.107658603267630839149905743220700757129758112923008798139070690203968518773909
Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/19.kmac_key_error/latest/run.log
UVM_ERROR @ 695502646 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 695502646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
27.kmac_sideload_invalid.33579327326456859966697657431259107674139331879676815713719553559377834986662
Line 84, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10065392246 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc663000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10065392246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
31.kmac_sideload_invalid.95183132539661120243886020290608881066975271628715922825177569768890416307804
Line 90, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10154933412 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xce881000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10154933412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
36.kmac_sideload_invalid.92578666122848614211266697131500253266460148413444424774341435858962494297220
Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10088949686 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9e4f8000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10088949686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
38.kmac_sideload_invalid.102812513393615312014707152881159229007620848373365048040784511259275644066525
Line 84, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10069405619 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1c9a7000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10069405619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
39.kmac_sideload_invalid.22008020838786039613319477401414469037968847747740842107410788692108755424448
Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/39.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10322526927 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x92741000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10322526927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
41.kmac_sideload_invalid.52170061507252501920429006320591557239225821234008602145309316334053579317107
Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10174155149 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x92e16000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10174155149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---