OTBN Simulation Results

Sunday September 21 2025 01:07:51 UTC

GitHub Revision: 1a5d173

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 21.345s 0 1 0.00
V1 single_binary otbn_single 21.207s 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 38.000s 1 5 20.00
V1 csr_rw otbn_csr_rw 38.000s 1 20 5.00
V1 csr_bit_bash otbn_csr_bit_bash 29.000s 1 5 20.00
V1 csr_aliasing otbn_csr_aliasing 38.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 50.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 38.000s 1 20 5.00
otbn_csr_aliasing 38.000s 0 5 0.00
V1 mem_walk otbn_mem_walk 38.000s 0 5 0.00
V1 mem_partial_access otbn_mem_partial_access 30.000s 0 5 0.00
V1 TOTAL 4 166 2.41
V2 reset_recovery otbn_reset 19.677s 0 10 0.00
V2 multi_error otbn_multi_err 20.564s 0 1 0.00
V2 back_to_back otbn_multi 21.378s 0 10 0.00
V2 stress_all otbn_stress_all 16.793s 0 10 0.00
V2 lc_escalation otbn_escalate 18.474s 0 60 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 14.374s 0 5 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 10.102s 0 10 0.00
V2 alert_test otbn_alert_test 50.000s 4 50 8.00
V2 intr_test otbn_intr_test 1.483m 2 50 4.00
V2 tl_d_oob_addr_access otbn_tl_errors 38.000s 0 20 0.00
V2 tl_d_illegal_access otbn_tl_errors 38.000s 0 20 0.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 38.000s 1 5 20.00
otbn_csr_rw 38.000s 1 20 5.00
otbn_csr_aliasing 38.000s 0 5 0.00
otbn_same_csr_outstanding 38.000s 2 20 10.00
V2 tl_d_partial_access otbn_csr_hw_reset 38.000s 1 5 20.00
otbn_csr_rw 38.000s 1 20 5.00
otbn_csr_aliasing 38.000s 0 5 0.00
otbn_same_csr_outstanding 38.000s 2 20 10.00
V2 TOTAL 8 246 3.25
V2S mem_integrity otbn_imem_err 19.361s 0 10 0.00
otbn_dmem_err 21.597s 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 33.033s 0 5 0.00
otbn_controller_ispr_rdata_err 18.716s 0 5 0.00
otbn_mac_bignum_acc_err 19.905s 0 5 0.00
otbn_urnd_err 12.569s 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 15.104s 0 5 0.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.616s 0 2 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 6.612s 0 10 0.00
V2S tl_intg_err otbn_sec_cm 30.000s 0 5 0.00
otbn_tl_intg_err 41.000s 2 20 10.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 42.000s 0 20 0.00
V2S prim_fsm_check otbn_sec_cm 30.000s 0 5 0.00
V2S prim_count_check otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_mem_scramble otbn_smoke 21.345s 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 21.597s 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 19.361s 0 10 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 41.000s 2 20 10.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 18.474s 0 60 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 19.361s 0 10 0.00
otbn_dmem_err 21.597s 0 15 0.00
otbn_zero_state_err_urnd 14.374s 0 5 0.00
otbn_illegal_mem_acc 15.104s 0 5 0.00
otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_scramble_key_sideload otbn_single 21.207s 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 19.361s 0 10 0.00
otbn_dmem_err 21.597s 0 15 0.00
otbn_zero_state_err_urnd 14.374s 0 5 0.00
otbn_illegal_mem_acc 15.104s 0 5 0.00
otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 18.474s 0 60 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 19.361s 0 10 0.00
otbn_dmem_err 21.597s 0 15 0.00
otbn_zero_state_err_urnd 14.374s 0 5 0.00
otbn_illegal_mem_acc 15.104s 0 5 0.00
otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 21.207s 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 9.623s 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 10.131s 0 5 0.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 10.107s 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 10.107s 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 16.608s 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 17.116s 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 30.000s 0 5 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 4.604s 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 4.604s 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 8.619s 0 7 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 21.207s 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 21.207s 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 21.207s 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 21.378s 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 21.207s 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 21.207s 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 6.495s 0 5 0.00
V2S sec_cm_key_sideload otbn_single 21.207s 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 30.000s 0 5 0.00
V2S TOTAL 2 163 1.23
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 13.312s 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 14 585 2.39

Failure Buckets