1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 46.000s | 3 | 50 | 6.00 | |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | pattgen_csr_rw | 50.000s | 0 | 20 | 0.00 | |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 46.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | pattgen_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 42.000s | 0 | 20 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 50.000s | 0 | 20 | 0.00 | |
| pattgen_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 3 | 105 | 2.86 | |||
| V2 | perf | pattgen_perf | 2.067m | 44.675ms | 1 | 50 | 2.00 |
| V2 | cnt_rollover | cnt_rollover | 58.000s | 0 | 50 | 0.00 | |
| V2 | error | pattgen_error | 1.267m | 2 | 50 | 4.00 | |
| V2 | stress_all | pattgen_stress_all | 46.000s | 0 | 50 | 0.00 | |
| V2 | alert_test | pattgen_alert_test | 46.000s | 1 | 50 | 2.00 | |
| V2 | intr_test | pattgen_intr_test | 46.000s | 3 | 50 | 6.00 | |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 47.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 47.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| pattgen_csr_rw | 50.000s | 0 | 20 | 0.00 | |||
| pattgen_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |||
| pattgen_same_csr_outstanding | 46.000s | 2 | 20 | 10.00 | |||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| pattgen_csr_rw | 50.000s | 0 | 20 | 0.00 | |||
| pattgen_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |||
| pattgen_same_csr_outstanding | 46.000s | 2 | 20 | 10.00 | |||
| V2 | TOTAL | 10 | 340 | 2.94 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 46.000s | 3 | 20 | 15.00 | |
| pattgen_sec_cm | 47.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 46.000s | 3 | 20 | 15.00 | |
| V2S | TOTAL | 3 | 25 | 12.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 1.900m | 23.506ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 42.000s | 2 | 50 | 4.00 | ||
| TOTAL | 18 | 570 | 3.16 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.17 | 100.00 | 100.00 | 100.00 | 97.57 | 95.40 | -- | 96.65 | 88.46 |
Job returned non-zero exit code has 545 failures:
0.pattgen_smoke.35127986071386976521802184972592499579239080755186288860986885692341781315742
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:02:48 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_smoke.60101754811529266575331617664347064323951654206806246090476046557606860999123
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:02:49 UTC (total: 00:00:26)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.pattgen_error.77297361733607591540059862495279154278538865118129888546527011036625883091201
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_error/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:02:54 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_error.69393126026511936866253185405889095475447345096753536021962159742494813887859
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_error/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:02:55 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
0.cnt_rollover.28397457019260852581547300786321979593802421762479445169143084636324363767942
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.cnt_rollover/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:02:47 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.cnt_rollover.35281947834747509015870859308635405019505224241081141228109852627154074063025
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.cnt_rollover/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:02:55 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 48 more failures.
0.pattgen_inactive_level.22403928429795832455583176065158447873384467916606037168232337281275767717762
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:02:39 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_inactive_level.91341185347256248514023238341270930727038824934057174545869493172959353396889
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:02:47 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
0.pattgen_tl_errors.102406582704400067508173511007083041406051094564645568972055142112067918443860
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_tl_errors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:08:22 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_tl_errors.65335836259710670754380936976179013505272783225145044417000922948111708995014
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_tl_errors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 21, 2025 at 07:08:30 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
2.pattgen_stress_all_with_rand_reset.111048570670250949297611299048780902180974605234381809570565171496180384059454
Line 177, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1265654865 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1265662726 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1265662726 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1265724580 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
19.pattgen_stress_all_with_rand_reset.41066704479301875149756829538904788925237355152502880759146916650245963643742
Line 112, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1634018315 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1634055945 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1634055945 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1634375945 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 4 more failures.
Job timed out after * minutes has 1 failures:
31.pattgen_stress_all.60687697301916417290642530349305431731455441402226557766678963958494663898433
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes