1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | prim_alert_request_test | prim_async_alert | 18.311s | 18 | 20 | 90.00 | |
| prim_async_fatal_alert | 26.353s | 19 | 20 | 95.00 | |||
| prim_sync_alert | 0.500s | 8.631us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 17.615s | 18 | 20 | 90.00 | |||
| V1 | prim_alert_test | prim_async_alert | 18.311s | 18 | 20 | 90.00 | |
| prim_async_fatal_alert | 26.353s | 19 | 20 | 95.00 | |||
| prim_sync_alert | 0.500s | 8.631us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 17.615s | 18 | 20 | 90.00 | |||
| V1 | prim_alert_ping_request_test | prim_async_alert | 18.311s | 18 | 20 | 90.00 | |
| prim_async_fatal_alert | 26.353s | 19 | 20 | 95.00 | |||
| prim_sync_alert | 0.500s | 8.631us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 17.615s | 18 | 20 | 90.00 | |||
| V1 | prim_alert_integrity_errors_test | prim_async_alert | 18.311s | 18 | 20 | 90.00 | |
| prim_async_fatal_alert | 26.353s | 19 | 20 | 95.00 | |||
| prim_sync_alert | 0.500s | 8.631us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 17.615s | 18 | 20 | 90.00 | |||
| V1 | TOTAL | 75 | 80 | 93.75 | |||
| V2 | prim_alert_init_trigger_test | prim_async_alert | 18.311s | 18 | 20 | 90.00 | |
| prim_async_fatal_alert | 26.353s | 19 | 20 | 95.00 | |||
| prim_sync_alert | 0.500s | 8.631us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 17.615s | 18 | 20 | 90.00 | |||
| Unmapped tests | prim_async_fatal_alert_with_3_cycles_skew | 20.292s | 19 | 20 | 95.00 | ||
| TOTAL | 94 | 100 | 94.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
|---|---|---|---|---|---|---|
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
Job returned non-zero exit code has 6 failures:
Test prim_async_alert has 2 failures.
6.prim_async_alert.68814711501682017068913885787073304101233121568243054423610369595101444030090
Log /nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_async_alert/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:19 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
8.prim_async_alert.65282858813169012296481475569821600725899413306075005681347037125889272299792
Log /nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_async_alert/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:19 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test prim_sync_fatal_alert has 2 failures.
6.prim_sync_fatal_alert.20094764634695416099218688190572874548010709745611231190156351912205181706953
Log /nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:19 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
18.prim_sync_fatal_alert.66150000615334558971050219348098166963365609267294196359446949015352050900036
Log /nightly/current_run/scratch/master/prim_alert-sim-vcs/18.prim_sync_fatal_alert/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:19 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test prim_async_fatal_alert has 1 failures.
13.prim_async_fatal_alert.49812186489255183229473636164156319746208342161342060998058881200262918785426
Log /nightly/current_run/scratch/master/prim_alert-sim-vcs/13.prim_async_fatal_alert/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:19 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test prim_async_fatal_alert_with_3_cycles_skew has 1 failures.
16.prim_async_fatal_alert_with_3_cycles_skew.28922277515840693856721860653053993494194033876580762679266171179014427999851
Log /nightly/current_run/scratch/master/prim_alert-sim-vcs/16.prim_async_fatal_alert_with_3_cycles_skew/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:19 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255