1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| Unmapped tests | prim_present_test | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 50 | 0.00 |
Job killed most likely because its dependent job failed. has 52 failures:
0.prim_present_test.80228064498463850120095763293525004791189599067759818754271229694304410927161
Log /nightly/current_run/scratch/master/prim_present-sim-vcs/0.prim_present_test/latest/run.log
1.prim_present_test.88508042906571312584500654507899475781759832812198013251839731409331733627886
Log /nightly/current_run/scratch/master/prim_present-sim-vcs/1.prim_present_test/latest/run.log
... and 48 more failures.
cov_merge
Log /nightly/current_run/scratch/master/prim_present-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /nightly/current_run/scratch/master/prim_present-sim-vcs/cov_report/cov_report.log
Job returned non-zero exit code has 1 failures:
default
Log /nightly/current_run/scratch/master/prim_present-sim-vcs/default/build.log
recompiling module prim_present_tb
All of 28 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 4.949 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1