PRIM_PRINCE Simulation Results

Sunday September 21 2025 01:07:51 UTC

GitHub Revision: 1a5d173

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
	Unmapped tests	prim_prince_test	43.460s	3.743ms	469	500	93.80
		TOTAL			469	500	93.80

Failure Buckets

• Job returned non-zero exit code has 29 failures:

  • Test prim_prince_test has 28 failures.

    • 20.prim_prince_test.3127954838058926158992026666430431927468218885477136301822946616445099904980
      Log /nightly/current_run/scratch/master/prim_prince-sim-vcs/20.prim_prince_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 21 01:10 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

    • 46.prim_prince_test.46888413805400565356658628936443108204016516370514314901583705258644760963524
      Log /nightly/current_run/scratch/master/prim_prince-sim-vcs/46.prim_prince_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 21 01:11 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

    • ... and 26 more failures.

  • Test prim_prince has 1 failures.

    • cov_report
      Log /nightly/current_run/scratch/master/prim_prince-sim-vcs/cov_report/cov_report.log

                    Inclusivity and Diversity" (Refer to article 000036315 at
                                https://solvnetplus.synopsys.com)
      
        Error-[URG-NLCW] No license key
          URG failed to get a license key. Number of attempts to get a license key
          exceeded the limit (500).
          Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
          file.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:236: cov_report] Error 1
      

• Job timed out after * minutes has 3 failures:

  • Test prim_prince_test has 3 failures.

    • 167.prim_prince_test.53141606987581282866223601531353960573706420704451327241781972209662100779431
      Log /nightly/current_run/scratch/master/prim_prince-sim-vcs/167.prim_prince_test/latest/run.log

        Job timed out after 60 minutes
      

    • 256.prim_prince_test.46172681373965958808048237032281326521298980063335607223481353354153854873778
      Log /nightly/current_run/scratch/master/prim_prince-sim-vcs/256.prim_prince_test/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 1 more failures.