1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 4.230s | 290.673us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 4.250s | 294.741us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 20.367s | 18 | 20 | 90.00 | |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 24.300s | 4 | 5 | 80.00 | |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 28.929s | 4 | 5 | 80.00 | |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.069s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 20.367s | 18 | 20 | 90.00 | |
| rom_ctrl_csr_aliasing | 28.929s | 4 | 5 | 80.00 | |||
| V1 | mem_walk | rom_ctrl_mem_walk | 22.838s | 4 | 5 | 80.00 | |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 4.620s | 597.972us | 5 | 5 | 100.00 |
| V1 | TOTAL | 60 | 67 | 89.55 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 4.790s | 182.219us | 2 | 2 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 20.521s | 18 | 20 | 90.00 | |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 6.630s | 1.173ms | 2 | 2 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 22.566s | 48 | 50 | 96.00 | |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 15.577s | 19 | 20 | 95.00 | |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 15.577s | 19 | 20 | 95.00 | |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 4.250s | 294.741us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 20.367s | 18 | 20 | 90.00 | |||
| rom_ctrl_csr_aliasing | 28.929s | 4 | 5 | 80.00 | |||
| rom_ctrl_same_csr_outstanding | 22.331s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 4.250s | 294.741us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 20.367s | 18 | 20 | 90.00 | |||
| rom_ctrl_csr_aliasing | 28.929s | 4 | 5 | 80.00 | |||
| rom_ctrl_same_csr_outstanding | 22.331s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 107 | 114 | 93.86 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 18.620s | 861.101us | 18 | 20 | 90.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 2.963m | 6.659ms | 1 | 5 | 20.00 |
| rom_ctrl_tl_intg_err | 45.510s | 3.235ms | 17 | 20 | 85.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 2.963m | 6.659ms | 1 | 5 | 20.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 2.963m | 6.659ms | 1 | 5 | 20.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 2.963m | 6.659ms | 1 | 5 | 20.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 2.963m | 6.659ms | 1 | 5 | 20.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 4.230s | 290.673us | 2 | 2 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 4.230s | 290.673us | 2 | 2 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 4.230s | 290.673us | 2 | 2 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 45.510s | 3.235ms | 17 | 20 | 85.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| rom_ctrl_kmac_err_chk | 6.630s | 1.173ms | 2 | 2 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 1.724m | 16.463ms | 17 | 20 | 85.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 18.620s | 861.101us | 18 | 20 | 90.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 2.963m | 6.659ms | 1 | 5 | 20.00 |
| V2S | TOTAL | 53 | 65 | 81.54 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 5.738m | 4.441ms | 20 | 20 | 100.00 |
| V3 | TOTAL | 20 | 20 | 100.00 | |||
| TOTAL | 240 | 266 | 90.23 |
Job returned non-zero exit code has 21 failures:
Test rom_ctrl_mem_walk has 1 failures.
0.rom_ctrl_mem_walk.70999106237950704165617386723617027200589829973303594853145249395977082610928
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_mem_walk/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:34 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_csr_aliasing has 1 failures.
1.rom_ctrl_csr_aliasing.13466680144943453889877214131340489802230598538835335717024155108606630895594
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:34 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_csr_bit_bash has 1 failures.
2.rom_ctrl_csr_bit_bash.60152278531461371665983312755806041966562509554740479496390180125581959551935
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:35 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_stress_all has 2 failures.
3.rom_ctrl_stress_all.24651747592895739273023362464772801537897864794673018629299556995011830253838
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
13.rom_ctrl_stress_all.24776841653868738005172597238681264439144891350882518784354112982685355891254
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_sec_cm has 1 failures.
4.rom_ctrl_sec_cm.19863133387806072037283790556919445240568684970951555667697238268231275593801
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 9 more tests.
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:
0.rom_ctrl_sec_cm.33759061693311641522347229249543219401031411630538802946617521666975227803382
Line 121, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 54470752ps failed at 54470752ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 54470752ps failed at 54470752ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
1.rom_ctrl_sec_cm.42000289821639740797726506221251275737614090358241400145931230686377562222769
Line 440, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 159222853ps failed at 159222853ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 159222853ps failed at 159222853ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
16.rom_ctrl_corrupt_sig_fatal_chk.99007292248218043754238786383081898784257496956756897000532374461086316045572
Line 96, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 7480042667 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 7480042667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rom_ctrl_corrupt_sig_fatal_chk.72417063724055582905795614256751995478166345486128743450658143678306892506751
Line 77, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 268236968 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 268236968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
3.rom_ctrl_sec_cm.42333147167823579259929099484369687941351835980672833865228599654812667744943
Line 432, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 373096584ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 373096584ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 373096584ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Job timed out after * minutes has 1 failures:
13.rom_ctrl_tl_intg_err.55838703251926531542034095714314756002395679979856781996119107450371312928196
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest/run.log
Job timed out after 60 minutes
Job killed most likely because its dependent job failed. has 1 failures: