1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 6.680s | 214.758us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 12.500s | 6.217ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 20.122s | 18 | 20 | 90.00 | |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 6.620s | 555.267us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 8.310s | 1.066ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 20.403s | 19 | 20 | 95.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 20.122s | 18 | 20 | 90.00 | |
| rom_ctrl_csr_aliasing | 8.310s | 1.066ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 8.380s | 1.045ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 6.760s | 288.108us | 5 | 5 | 100.00 |
| V1 | TOTAL | 64 | 67 | 95.52 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 7.780s | 315.836us | 2 | 2 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 39.470s | 4.141ms | 19 | 20 | 95.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 18.270s | 39.264ms | 2 | 2 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 32.208s | 47 | 50 | 94.00 | |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 16.160s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 16.160s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 12.500s | 6.217ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 20.122s | 18 | 20 | 90.00 | |||
| rom_ctrl_csr_aliasing | 8.310s | 1.066ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 24.419s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 12.500s | 6.217ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 20.122s | 18 | 20 | 90.00 | |||
| rom_ctrl_csr_aliasing | 8.310s | 1.066ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 24.419s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 106 | 114 | 92.98 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 37.860s | 1.618ms | 18 | 20 | 90.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 7.166m | 1.021ms | 2 | 5 | 40.00 |
| rom_ctrl_tl_intg_err | 1.549m | 4.866ms | 19 | 20 | 95.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 7.166m | 1.021ms | 2 | 5 | 40.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 7.166m | 1.021ms | 2 | 5 | 40.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 7.166m | 1.021ms | 2 | 5 | 40.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 7.166m | 1.021ms | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 6.680s | 214.758us | 2 | 2 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 6.680s | 214.758us | 2 | 2 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 6.680s | 214.758us | 2 | 2 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.549m | 4.866ms | 19 | 20 | 95.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| rom_ctrl_kmac_err_chk | 18.270s | 39.264ms | 2 | 2 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 3.707m | 33.082ms | 18 | 20 | 90.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 37.860s | 1.618ms | 18 | 20 | 90.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 7.166m | 1.021ms | 2 | 5 | 40.00 |
| V2S | TOTAL | 57 | 65 | 87.69 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 4.481m | 4.945ms | 17 | 20 | 85.00 |
| V3 | TOTAL | 17 | 20 | 85.00 | |||
| TOTAL | 244 | 266 | 91.73 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.00 | 99.59 | 98.07 | 100.00 | 100.00 | 99.27 | 96.80 | 99.28 |
Job returned non-zero exit code has 18 failures:
Test rom_ctrl_tl_intg_err has 1 failures.
0.rom_ctrl_tl_intg_err.88240587152648051298732517538359270797280315342402963400200722018742774579326
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_same_csr_outstanding has 2 failures.
0.rom_ctrl_same_csr_outstanding.36978910283148211704896804012507798115669217791786324227142087541465030342800
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
16.rom_ctrl_same_csr_outstanding.112326024726335479980508386955566753920160585908614258282704355436491629588908
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:37 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
0.rom_ctrl_csr_mem_rw_with_rand_reset.16755786750220094873923487075972892987088779958433408728900851547563077177
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
4.rom_ctrl_stress_all_with_rand_reset.74629980293871495479281746095023619193679589576471970523767513915213963999865
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
17.rom_ctrl_stress_all_with_rand_reset.42475224561872450074972213385537033554556231789845891019583851797318330267436
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:46 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_alert_test has 3 failures.
4.rom_ctrl_alert_test.70750237218351884671757825554763862285068537401720396444278930911034052689284
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
12.rom_ctrl_alert_test.72878640390406952381006855914646974789023175076541128860363483825099014925812
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:46 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
... and 5 more tests.
Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
0.rom_ctrl_sec_cm.56565769370452735022161099817238563337844323453622596094891933879297916409692
Line 376, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 58958359ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 58958359ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 58958359ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
1.rom_ctrl_sec_cm.90824397637288805647312029804510388637268464429268422197576794628181678154173
Line 179, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 82747696ps failed at 82747696ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 82747696ps failed at 82747696ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
2.rom_ctrl_sec_cm.6644190995273947948448791895111883741048442132717369266013029046875908168183
Line 303, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 67206996ps failed at 67206996ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 67246996ps failed at 67246996ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Job timed out after * minutes has 1 failures:
5.rom_ctrl_stress_all_with_rand_reset.52052746238719788713500554382968422774901260660034704901693809769350218566308
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes