1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 32.558s | 18 | 20 | 90.00 | |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.570s | 15.138us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 18.470s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.440s | 833.031us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.720s | 33.818us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 20.033s | 19 | 20 | 95.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 18.470s | 19 | 20 | 95.00 | |
| rv_timer_csr_aliasing | 0.720s | 33.818us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 71 | 75 | 94.67 | |||
| V2 | random_reset | rv_timer_random_reset | 26.148s | 1 | 20 | 5.00 | |
| V2 | disabled | rv_timer_disabled | 2.120s | 1.838ms | 20 | 20 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 8.955m | 1.858s | 10 | 10 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 8.955m | 1.858s | 10 | 10 | 100.00 |
| V2 | stress | rv_timer_stress_all | 5.610s | 4.468ms | 20 | 20 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 28.819s | 49 | 50 | 98.00 | |
| V2 | intr_test | rv_timer_intr_test | 0.580s | 25.984us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.070s | 608.757us | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.070s | 608.757us | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.570s | 15.138us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 18.470s | 19 | 20 | 95.00 | |||
| rv_timer_csr_aliasing | 0.720s | 33.818us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 22.510s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.570s | 15.138us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 18.470s | 19 | 20 | 95.00 | |||
| rv_timer_csr_aliasing | 0.720s | 33.818us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 22.510s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 187 | 210 | 89.05 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.810s | 206.679us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 33.046s | 19 | 20 | 95.00 | |||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 33.046s | 19 | 20 | 95.00 | |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | min_value | rv_timer_min | 20.357s | 3 | 10 | 30.00 | |
| V3 | max_value | rv_timer_max | 0.630s | 605.410us | 1 | 10 | 10.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 54.750s | 7.533ms | 11 | 20 | 55.00 |
| V3 | TOTAL | 15 | 40 | 37.50 | |||
| TOTAL | 297 | 350 | 84.86 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 22 failures:
0.rv_timer_min.112250547876402192847584945050028568857396482138540980980565339592123787540725
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 65272871 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2d545304) == 0x1
UVM_INFO @ 65272871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_min.82458136130793982937348646484818025099259797716312938912791076527875922322789
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
UVM_FATAL @ 514668380 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x967a6104) == 0x1
UVM_INFO @ 514668380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
0.rv_timer_random_reset.12525710851939753923702037875055880059094363706973871620537791534087111637847
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 156053103 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7bcd7704) == 0x1
UVM_INFO @ 156053103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_random_reset.81618469187725563684367391774949000584197823344281830205853956343382721974084
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 926929429 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8f2b5704) == 0x1
UVM_INFO @ 926929429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
Job returned non-zero exit code has 14 failures:
Test rv_timer_min has 2 failures.
2.rv_timer_min.21013101330517024611309652556316135449465173652470659045905254048118368260433
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
5.rv_timer_min.4056159230666259613826049569145364817313943416329597765651842749638046202830
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_min/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_timer_alert_test has 1 failures.
5.rv_timer_alert_test.103131171862941468186015875488084176872775649424098267255145521674703828794128
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_timer_random_reset has 2 failures.
6.rv_timer_random_reset.10447531702341184191823329989784606153085707050248601560099168271466325711702
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/6.rv_timer_random_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
12.rv_timer_random_reset.12568614321173133371488324495933495674941018360656243722555892187450474116471
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/12.rv_timer_random_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_timer_tl_intg_err has 1 failures.
7.rv_timer_tl_intg_err.114443728698212884486479002030072268703350107707362991559545184213248451357049
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:48 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_timer_same_csr_outstanding has 1 failures.
11.rv_timer_same_csr_outstanding.74046282174077446864700081231377628366410243243669704542368167856575354778655
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:48 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more tests.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
0.rv_timer_max.114697868265026247723596517462680329274477519729983079425796423161288336137263
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 51758361 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 51758361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_max.90018229673293598322156191016825340845205814929444348746208352439824682279208
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
UVM_ERROR @ 70240626 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 70240626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:870) [rv_timer_common_vseq] Check failed (vseq_done) has 5 failures:
3.rv_timer_stress_all_with_rand_reset.113095820062217518652358697517214725090935108666779849694423997985385063643250
Line 192, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1611631671 ps: (cip_base_vseq.sv:870) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1611631671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_timer_stress_all_with_rand_reset.111704382554432488238738782882770897917745213601841018660175464435179639040693
Line 132, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 9057145030 ps: (cip_base_vseq.sv:870) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 9057145030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job timed out after * minutes has 2 failures:
Test rv_timer_tl_errors has 1 failures.
8.rv_timer_tl_errors.65910340106758987717807663285551578277085108634794171116732612849634147341370
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest/run.log
Job timed out after 60 minutes
Test rv_timer_same_csr_outstanding has 1 failures.
19.rv_timer_same_csr_outstanding.12352324476500099079878225701662856053150423025810676785275698162495027150203
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:
10.rv_timer_stress_all_with_rand_reset.36334937806300766771149511271742520142982095435039232318954110019861985735503
Line 274, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/10.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17778287914 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 17778287914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rv_timer_stress_all_with_rand_reset.103265320224302565369747306371422749475957238399943103240623674009518135952342
Line 196, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/16.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10386823282 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 10386823282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: